106 	address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);  in soc15_uvd_ctx_rreg()
107 	data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);  in soc15_uvd_ctx_rreg()
120 	address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);  in soc15_uvd_ctx_wreg()
121 	data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);  in soc15_uvd_ctx_wreg()
134 	address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);  in soc15_didt_rreg()
135 	data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);  in soc15_didt_rreg()
148 	address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);  in soc15_didt_wreg()
149 	data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);  in soc15_didt_wreg()
221 	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);  in soc15_grbm_select()
253 	WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);  in soc15_read_bios_from_rom()
256 		dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));  in soc15_read_bios_from_rom()
316 		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))  in soc15_get_register_value()
318 		else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))  in soc15_get_register_value()
580 		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(  in soc15_invalidate_hdp()
825 	def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));  in soc15_update_hdp_light_sleep()
833 		WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);  in soc15_update_hdp_light_sleep()
840 	def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));  in soc15_update_drm_clock_gating()
862 		WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);  in soc15_update_drm_clock_gating()
869 	def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));  in soc15_update_drm_light_sleep()
877 		WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);  in soc15_update_drm_light_sleep()
885 	def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));  in soc15_update_rom_medium_grain_clock_gating()
895 		WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);  in soc15_update_rom_medium_grain_clock_gating()
956 	data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));  in soc15_common_get_clockgating_state()
961 	data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));  in soc15_common_get_clockgating_state()
966 	data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));  in soc15_common_get_clockgating_state()
971 	data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));  in soc15_common_get_clockgating_state()