Lines Matching refs:ih
40 adev->irq.ih.enabled = true; in si_ih_enable_interrupts()
54 adev->irq.ih.enabled = false; in si_ih_disable_interrupts()
55 adev->irq.ih.rptr = 0; in si_ih_disable_interrupts()
65 WREG32(INTERRUPT_CNTL2, adev->irq.ih.gpu_addr >> 8); in si_ih_irq_init()
71 WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in si_ih_irq_init()
72 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in si_ih_irq_init()
79 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in si_ih_irq_init()
107 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in si_ih_get_wptr()
112 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in si_ih_get_wptr()
113 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in si_ih_get_wptr()
118 return (wptr & adev->irq.ih.ptr_mask); in si_ih_get_wptr()
137 u32 ring_index = adev->irq.ih.rptr >> 2; in si_ih_decode_iv()
140 dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); in si_ih_decode_iv()
141 dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); in si_ih_decode_iv()
142 dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); in si_ih_decode_iv()
143 dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); in si_ih_decode_iv()
151 adev->irq.ih.rptr += 16; in si_ih_decode_iv()
156 WREG32(IH_RB_RPTR, adev->irq.ih.rptr); in si_ih_set_rptr()