5097 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_populate_ulv_state()  local
5101 	ret = si_convert_power_level_to_smc(adev, &ulv->pl,  in si_populate_ulv_state()
5110 		if (ulv->one_pcie_lane_in_ulv)  in si_populate_ulv_state()
5126 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_program_ulv_memory_timing_parameters()  local
5130 	ret = si_populate_memory_timing_parameters(adev, &ulv->pl,  in si_program_ulv_memory_timing_parameters()
5136 				   ulv->volt_change_delay);  in si_program_ulv_memory_timing_parameters()
5160 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_init_smc_table()  local
5220 	if (ulv->supported && ulv->pl.vddc) {  in si_init_smc_table()
5229 		WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);  in si_init_smc_table()
5230 		WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);  in si_init_smc_table()
5599 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_disable_ulv()  local
5601 	if (ulv->supported)  in si_disable_ulv()
5612 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_is_state_ulv_compatible()  local
5616 	if (state->performance_levels[0].mclk != ulv->pl.mclk)  in si_is_state_ulv_compatible()
5624 			if (ulv->pl.vddc <  in si_is_state_ulv_compatible()
5640 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_set_power_state_conditionally_enable_ulv()  local
5642 	if (ulv->supported) {  in si_set_power_state_conditionally_enable_ulv()
5756 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_upload_ulv_state()  local
5759 	if (ulv->supported && ulv->pl.vddc) {  in si_upload_ulv_state()
6109 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_populate_mc_reg_table()  local
6126 	if (ulv->supported && ulv->pl.vddc != 0)  in si_populate_mc_reg_table()
6127 		si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,  in si_populate_mc_reg_table()
7171 		si_pi->ulv.supported = false;  in si_parse_pplib_clock_info()
7172 		si_pi->ulv.pl = *pl;  in si_parse_pplib_clock_info()
7173 		si_pi->ulv.one_pcie_lane_in_ulv = false;  in si_parse_pplib_clock_info()
7174 		si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;  in si_parse_pplib_clock_info()
7175 		si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;  in si_parse_pplib_clock_info()
7176 		si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;  in si_parse_pplib_clock_info()