1981 	struct si_power_info *si_pi = si_get_pi(adev);  in si_initialize_powertune_defaults()  local
1985 		si_pi->cac_weights = cac_weights_tahiti;  in si_initialize_powertune_defaults()
1986 		si_pi->lcac_config = lcac_tahiti;  in si_initialize_powertune_defaults()
1987 		si_pi->cac_override = cac_override_tahiti;  in si_initialize_powertune_defaults()
1988 		si_pi->powertune_data = &powertune_data_tahiti;  in si_initialize_powertune_defaults()
1989 		si_pi->dte_data = dte_data_tahiti;  in si_initialize_powertune_defaults()
1993 			si_pi->dte_data.enable_dte_by_default = true;  in si_initialize_powertune_defaults()
1996 			si_pi->dte_data = dte_data_new_zealand;  in si_initialize_powertune_defaults()
2002 			si_pi->dte_data = dte_data_aruba_pro;  in si_initialize_powertune_defaults()
2006 			si_pi->dte_data = dte_data_malta;  in si_initialize_powertune_defaults()
2010 			si_pi->dte_data = dte_data_tahiti_pro;  in si_initialize_powertune_defaults()
2014 			if (si_pi->dte_data.enable_dte_by_default == true)  in si_initialize_powertune_defaults()
2019 		si_pi->cac_weights = cac_weights_pitcairn;  in si_initialize_powertune_defaults()
2020 		si_pi->lcac_config = lcac_pitcairn;  in si_initialize_powertune_defaults()
2021 		si_pi->cac_override = cac_override_pitcairn;  in si_initialize_powertune_defaults()
2022 		si_pi->powertune_data = &powertune_data_pitcairn;  in si_initialize_powertune_defaults()
2027 			si_pi->dte_data = dte_data_curacao_xt;  in si_initialize_powertune_defaults()
2032 			si_pi->dte_data = dte_data_curacao_pro;  in si_initialize_powertune_defaults()
2037 			si_pi->dte_data = dte_data_neptune_xt;  in si_initialize_powertune_defaults()
2041 			si_pi->dte_data = dte_data_pitcairn;  in si_initialize_powertune_defaults()
2045 		si_pi->lcac_config = lcac_cape_verde;  in si_initialize_powertune_defaults()
2046 		si_pi->cac_override = cac_override_cape_verde;  in si_initialize_powertune_defaults()
2047 		si_pi->powertune_data = &powertune_data_cape_verde;  in si_initialize_powertune_defaults()
2054 			si_pi->cac_weights = cac_weights_cape_verde_pro;  in si_initialize_powertune_defaults()
2055 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
2058 			si_pi->cac_weights = cac_weights_cape_verde_pro;  in si_initialize_powertune_defaults()
2059 			si_pi->dte_data = dte_data_sun_xt;  in si_initialize_powertune_defaults()
2064 			si_pi->cac_weights = cac_weights_heathrow;  in si_initialize_powertune_defaults()
2065 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
2069 			si_pi->cac_weights = cac_weights_chelsea_xt;  in si_initialize_powertune_defaults()
2070 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
2073 			si_pi->cac_weights = cac_weights_chelsea_pro;  in si_initialize_powertune_defaults()
2074 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
2077 			si_pi->cac_weights = cac_weights_heathrow;  in si_initialize_powertune_defaults()
2078 			si_pi->dte_data = dte_data_venus_xtx;  in si_initialize_powertune_defaults()
2081 			si_pi->cac_weights = cac_weights_heathrow;  in si_initialize_powertune_defaults()
2082 			si_pi->dte_data = dte_data_venus_xt;  in si_initialize_powertune_defaults()
2088 			si_pi->cac_weights = cac_weights_chelsea_pro;  in si_initialize_powertune_defaults()
2089 			si_pi->dte_data = dte_data_venus_pro;  in si_initialize_powertune_defaults()
2092 			si_pi->cac_weights = cac_weights_cape_verde;  in si_initialize_powertune_defaults()
2093 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
2097 		si_pi->lcac_config = lcac_mars_pro;  in si_initialize_powertune_defaults()
2098 		si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2099 		si_pi->powertune_data = &powertune_data_mars_pro;  in si_initialize_powertune_defaults()
2100 		si_pi->dte_data = dte_data_mars_pro;  in si_initialize_powertune_defaults()
2107 			si_pi->cac_weights = cac_weights_mars_pro;  in si_initialize_powertune_defaults()
2114 			si_pi->cac_weights = cac_weights_mars_xt;  in si_initialize_powertune_defaults()
2120 			si_pi->cac_weights = cac_weights_oland_pro;  in si_initialize_powertune_defaults()
2124 			si_pi->cac_weights = cac_weights_oland_xt;  in si_initialize_powertune_defaults()
2128 			si_pi->cac_weights = cac_weights_oland;  in si_initialize_powertune_defaults()
2129 			si_pi->lcac_config = lcac_oland;  in si_initialize_powertune_defaults()
2130 			si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2131 			si_pi->powertune_data = &powertune_data_oland;  in si_initialize_powertune_defaults()
2132 			si_pi->dte_data = dte_data_oland;  in si_initialize_powertune_defaults()
2136 		si_pi->cac_weights = cac_weights_hainan;  in si_initialize_powertune_defaults()
2137 		si_pi->lcac_config = lcac_oland;  in si_initialize_powertune_defaults()
2138 		si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2139 		si_pi->powertune_data = &powertune_data_hainan;  in si_initialize_powertune_defaults()
2140 		si_pi->dte_data = dte_data_sun_xt;  in si_initialize_powertune_defaults()
2150 	si_pi->enable_dte = false;  in si_initialize_powertune_defaults()
2152 	if (si_pi->powertune_data->enable_powertune_by_default) {  in si_initialize_powertune_defaults()
2155 		if (si_pi->dte_data.enable_dte_by_default) {  in si_initialize_powertune_defaults()
2156 			si_pi->enable_dte = true;  in si_initialize_powertune_defaults()
2158 				si_update_dte_from_pl2(adev, &si_pi->dte_data);  in si_initialize_powertune_defaults()
2169 		si_pi->dyn_powertune_data.l2_lta_window_size =  in si_initialize_powertune_defaults()
2170 			si_pi->powertune_data->l2_lta_window_size_default;  in si_initialize_powertune_defaults()
2171 		si_pi->dyn_powertune_data.lts_truncate =  in si_initialize_powertune_defaults()
2172 			si_pi->powertune_data->lts_truncate_default;  in si_initialize_powertune_defaults()
2175 		si_pi->dyn_powertune_data.l2_lta_window_size = 0;  in si_initialize_powertune_defaults()
2176 		si_pi->dyn_powertune_data.lts_truncate = 0;  in si_initialize_powertune_defaults()
2179 	si_pi->dyn_powertune_data.disable_uvd_powertune = false;  in si_initialize_powertune_defaults()
2249 	struct si_power_info *si_pi = si_get_pi(adev);  in si_populate_smc_tdp_limits()  local
2252 		SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;  in si_populate_smc_tdp_limits()
2281 						  (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +  in si_populate_smc_tdp_limits()
2285 						  si_pi->sram_end);  in si_populate_smc_tdp_limits()
2289 		if (si_pi->enable_ppm) {  in si_populate_smc_tdp_limits()
2290 			papm_parm = &si_pi->papm_parm;  in si_populate_smc_tdp_limits()
2299 			ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,  in si_populate_smc_tdp_limits()
2302 							  si_pi->sram_end);  in si_populate_smc_tdp_limits()
2314 	struct si_power_info *si_pi = si_get_pi(adev);  in si_populate_smc_tdp_limits_2()  local
2317 		SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;  in si_populate_smc_tdp_limits_2()
2329 						  (si_pi->state_table_start +  in si_populate_smc_tdp_limits_2()
2334 						  si_pi->sram_end);  in si_populate_smc_tdp_limits_2()
2367 	struct si_power_info *si_pi = si_get_pi(adev);  in si_should_disable_uvd_powertune()  local
2369 	if (si_pi->dyn_powertune_data.disable_uvd_powertune &&  in si_should_disable_uvd_powertune()
2565 	struct si_power_info *si_pi = si_get_pi(adev);  in si_initialize_smc_dte_tables()  local
2567 	struct si_dte_data *dte_data = &si_pi->dte_data;  in si_initialize_smc_dte_tables()
2574 		si_pi->enable_dte = false;  in si_initialize_smc_dte_tables()
2576 	if (si_pi->enable_dte == false)  in si_initialize_smc_dte_tables()
2584 		si_pi->enable_dte = false;  in si_initialize_smc_dte_tables()
2621 	ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,  in si_initialize_smc_dte_tables()
2624 					  si_pi->sram_end);  in si_initialize_smc_dte_tables()
2633 	struct si_power_info *si_pi = si_get_pi(adev);  in si_get_cac_std_voltage_max_min()  local
2652 	if (si_pi->powertune_data->lkge_lut_v0_percent > 100)  in si_get_cac_std_voltage_max_min()
2655 	v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;  in si_get_cac_std_voltage_max_min()
2679 	struct si_power_info *si_pi = si_get_pi(adev);  in si_init_dte_leakage_table()  local
2696 							 &si_pi->powertune_data->leakage_coefficients,  in si_init_dte_leakage_table()
2699 							 si_pi->dyn_powertune_data.cac_leakage,  in si_init_dte_leakage_table()
2718 	struct si_power_info *si_pi = si_get_pi(adev);  in si_init_simplified_leakage_table()  local
2731 					   &si_pi->powertune_data->leakage_coefficients,  in si_init_simplified_leakage_table()
2732 					   si_pi->powertune_data->fixed_kt,  in si_init_simplified_leakage_table()
2734 					   si_pi->dyn_powertune_data.cac_leakage,  in si_init_simplified_leakage_table()
2752 	struct si_power_info *si_pi = si_get_pi(adev);  in si_initialize_smc_cac_tables()  local
2768 	reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);  in si_initialize_smc_cac_tables()
2771 	si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;  in si_initialize_smc_cac_tables()
2772 	si_pi->dyn_powertune_data.dc_pwr_value =  in si_initialize_smc_cac_tables()
2773 		si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];  in si_initialize_smc_cac_tables()
2774 	si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);  in si_initialize_smc_cac_tables()
2775 	si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;  in si_initialize_smc_cac_tables()
2777 	si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;  in si_initialize_smc_cac_tables()
2788 	if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)  in si_initialize_smc_cac_tables()
2800 	cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);  in si_initialize_smc_cac_tables()
2801 	cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;  in si_initialize_smc_cac_tables()
2802 	cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;  in si_initialize_smc_cac_tables()
2806 	cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);  in si_initialize_smc_cac_tables()
2810 	cac_tables->cac_temp = si_pi->powertune_data->operating_temp;  in si_initialize_smc_cac_tables()
2814 	ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,  in si_initialize_smc_cac_tables()
2817 					  si_pi->sram_end);  in si_initialize_smc_cac_tables()
2877 	struct si_power_info *si_pi = si_get_pi(adev);  in si_initialize_hardware_cac_manager()  local
2884 	ret = si_program_cac_config_registers(adev, si_pi->lcac_config);  in si_initialize_hardware_cac_manager()
2887 	ret = si_program_cac_config_registers(adev, si_pi->cac_override);  in si_initialize_hardware_cac_manager()
2890 	ret = si_program_cac_config_registers(adev, si_pi->cac_weights);  in si_initialize_hardware_cac_manager()
2902 	struct si_power_info *si_pi = si_get_pi(adev);  in si_enable_smc_cac()  local
2923 				if (si_pi->enable_dte) {  in si_enable_smc_cac()
2930 			if (si_pi->enable_dte)  in si_enable_smc_cac()
2947 	struct si_power_info *si_pi = si_get_pi(adev);  in si_init_smc_spll_table()  local
2957 	if (si_pi->spll_table_start == 0)  in si_init_smc_spll_table()
3002 		ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,  in si_init_smc_spll_table()
3005 						  si_pi->sram_end);  in si_init_smc_spll_table()
3019 	struct si_power_info *si_pi = si_get_pi(adev);  in si_get_lower_of_leakage_and_vce_voltage()  local
3022 	for (i = 0; i < si_pi->leakage_voltage.count; i++){  in si_get_lower_of_leakage_and_vce_voltage()
3023 		if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)  in si_get_lower_of_leakage_and_vce_voltage()
3024 			highest_leakage = si_pi->leakage_voltage.entries[i].voltage;  in si_get_lower_of_leakage_and_vce_voltage()
3027 	if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))  in si_get_lower_of_leakage_and_vce_voltage()
3644 	struct si_power_info *si_pi = si_get_pi(adev);
3647 					     si_pi->soft_regs_start + reg_offset, value,
3648 					     si_pi->sram_end);
3655 	struct si_power_info *si_pi = si_get_pi(adev);  in si_write_smc_soft_register()  local
3658 					      si_pi->soft_regs_start + reg_offset,  in si_write_smc_soft_register()
3659 					      value, si_pi->sram_end);  in si_write_smc_soft_register()
3692 	struct si_power_info *si_pi = si_get_pi(adev);  in si_get_leakage_vddc()  local
3700 			si_pi->leakage_voltage.entries[count].voltage = vddc;  in si_get_leakage_vddc()
3701 			si_pi->leakage_voltage.entries[count].leakage_index =  in si_get_leakage_vddc()
3706 	si_pi->leakage_voltage.count = count;  in si_get_leakage_vddc()
3712 	struct si_power_info *si_pi = si_get_pi(adev);  in si_get_leakage_voltage_from_leakage_index()  local
3727 	for (i = 0; i < si_pi->leakage_voltage.count; i++) {  in si_get_leakage_voltage_from_leakage_index()
3728 		if (si_pi->leakage_voltage.entries[i].leakage_index == index) {  in si_get_leakage_voltage_from_leakage_index()
3729 			*leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;  in si_get_leakage_voltage_from_leakage_index()
3938 	struct si_power_info *si_pi = si_get_pi(adev);  in si_process_firmware_header()  local
3945 					    &tmp, si_pi->sram_end);  in si_process_firmware_header()
3949 	si_pi->state_table_start = tmp;  in si_process_firmware_header()
3954 					    &tmp, si_pi->sram_end);  in si_process_firmware_header()
3958 	si_pi->soft_regs_start = tmp;  in si_process_firmware_header()
3963 					    &tmp, si_pi->sram_end);  in si_process_firmware_header()
3967 	si_pi->mc_reg_table_start = tmp;  in si_process_firmware_header()
3972 					    &tmp, si_pi->sram_end);  in si_process_firmware_header()
3976 	si_pi->fan_table_start = tmp;  in si_process_firmware_header()
3981 					    &tmp, si_pi->sram_end);  in si_process_firmware_header()
3985 	si_pi->arb_table_start = tmp;  in si_process_firmware_header()
3990 					    &tmp, si_pi->sram_end);  in si_process_firmware_header()
3994 	si_pi->cac_table_start = tmp;  in si_process_firmware_header()
3999 					    &tmp, si_pi->sram_end);  in si_process_firmware_header()
4003 	si_pi->dte_table_start = tmp;  in si_process_firmware_header()
4008 					    &tmp, si_pi->sram_end);  in si_process_firmware_header()
4012 	si_pi->spll_table_start = tmp;  in si_process_firmware_header()
4017 					    &tmp, si_pi->sram_end);  in si_process_firmware_header()
4021 	si_pi->papm_cfg_table_start = tmp;  in si_process_firmware_header()
4028 	struct si_power_info *si_pi = si_get_pi(adev);  in si_read_clock_registers()  local
4030 	si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);  in si_read_clock_registers()
4031 	si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);  in si_read_clock_registers()
4032 	si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);  in si_read_clock_registers()
4033 	si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);  in si_read_clock_registers()
4034 	si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);  in si_read_clock_registers()
4035 	si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);  in si_read_clock_registers()
4036 	si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);  in si_read_clock_registers()
4037 	si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);  in si_read_clock_registers()
4038 	si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);  in si_read_clock_registers()
4039 	si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);  in si_read_clock_registers()
4040 	si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);  in si_read_clock_registers()
4041 	si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);  in si_read_clock_registers()
4042 	si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);  in si_read_clock_registers()
4043 	si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);  in si_read_clock_registers()
4044 	si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);  in si_read_clock_registers()
4346 	struct si_power_info *si_pi = si_get_pi(adev);  in si_upload_firmware()  local
4351 	return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);  in si_upload_firmware()
4423 	struct si_power_info *si_pi = si_get_pi(adev);  in si_construct_voltage_tables()  local
4436 	} else if (si_pi->voltage_control_svi2) {  in si_construct_voltage_tables()
4457 	if (si_pi->vddci_control_svi2) {  in si_construct_voltage_tables()
4467 						    VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);  in si_construct_voltage_tables()
4474 		if (si_pi->mvdd_voltage_table.count == 0) {  in si_construct_voltage_tables()
4479 		if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)  in si_construct_voltage_tables()
4482 								 &si_pi->mvdd_voltage_table);  in si_construct_voltage_tables()
4485 	if (si_pi->vddc_phase_shed_control) {  in si_construct_voltage_tables()
4487 						    VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);  in si_construct_voltage_tables()
4489 			si_pi->vddc_phase_shed_control = false;  in si_construct_voltage_tables()
4491 		if ((si_pi->vddc_phase_shed_table.count == 0) ||  in si_construct_voltage_tables()
4492 		    (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))  in si_construct_voltage_tables()
4493 			si_pi->vddc_phase_shed_control = false;  in si_construct_voltage_tables()
4514 	struct si_power_info *si_pi = si_get_pi(adev);  in si_populate_smc_voltage_tables()  local
4517 	if (si_pi->voltage_control_svi2) {  in si_populate_smc_voltage_tables()
4519 			si_pi->svc_gpio_id);  in si_populate_smc_voltage_tables()
4521 			si_pi->svd_gpio_id);  in si_populate_smc_voltage_tables()
4546 		if (si_pi->mvdd_voltage_table.count) {  in si_populate_smc_voltage_tables()
4547 			si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);  in si_populate_smc_voltage_tables()
4550 				cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);  in si_populate_smc_voltage_tables()
4553 		if (si_pi->vddc_phase_shed_control) {  in si_populate_smc_voltage_tables()
4554 			if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,  in si_populate_smc_voltage_tables()
4556 				si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);  in si_populate_smc_voltage_tables()
4559 					cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);  in si_populate_smc_voltage_tables()
4562 							   (u32)si_pi->vddc_phase_shed_table.phase_delay);  in si_populate_smc_voltage_tables()
4564 				si_pi->vddc_phase_shed_control = false;  in si_populate_smc_voltage_tables()
4596 	struct si_power_info *si_pi = si_get_pi(adev);  in si_populate_mvdd_value()  local
4602 			voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;  in si_populate_mvdd_value()
4604 		voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);  in si_populate_mvdd_value()
4691 	struct si_power_info *si_pi = si_get_pi(adev);  in si_init_arb_table_index()  local
4695 	ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,  in si_init_arb_table_index()
4696 					    &tmp, si_pi->sram_end);  in si_init_arb_table_index()
4703 	return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,  in si_init_arb_table_index()
4704 					      tmp, si_pi->sram_end);  in si_init_arb_table_index()
4720 	struct si_power_info *si_pi = si_get_pi(adev);  in si_force_switch_to_arb_f0()  local
4724 	ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,  in si_force_switch_to_arb_f0()
4725 					    &tmp, si_pi->sram_end);  in si_force_switch_to_arb_f0()
4786 	struct si_power_info *si_pi = si_get_pi(adev);  in si_do_program_memory_timing_parameters()  local
4796 						  si_pi->arb_table_start +  in si_do_program_memory_timing_parameters()
4801 						  si_pi->sram_end);  in si_do_program_memory_timing_parameters()
4820 	struct si_power_info *si_pi = si_get_pi(adev);  in si_populate_initial_mvdd_value()  local
4823 		return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,  in si_populate_initial_mvdd_value()
4824 						 si_pi->mvdd_bootup_value, voltage);  in si_populate_initial_mvdd_value()
4836 	struct si_power_info *si_pi = si_get_pi(adev);  in si_populate_smc_initial_state()  local
4841 		cpu_to_be32(si_pi->clock_registers.dll_cntl);  in si_populate_smc_initial_state()
4843 		cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);  in si_populate_smc_initial_state()
4845 		cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);  in si_populate_smc_initial_state()
4847 		cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);  in si_populate_smc_initial_state()
4849 		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);  in si_populate_smc_initial_state()
4851 		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);  in si_populate_smc_initial_state()
4853 		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);  in si_populate_smc_initial_state()
4855 		cpu_to_be32(si_pi->clock_registers.mpll_ss1);  in si_populate_smc_initial_state()
4857 		cpu_to_be32(si_pi->clock_registers.mpll_ss2);  in si_populate_smc_initial_state()
4863 		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);  in si_populate_smc_initial_state()
4865 		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);  in si_populate_smc_initial_state()
4867 		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);  in si_populate_smc_initial_state()
4869 		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);  in si_populate_smc_initial_state()
4871 		cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);  in si_populate_smc_initial_state()
4873 		cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);  in si_populate_smc_initial_state()
4905 	if (si_pi->vddc_phase_shed_control)  in si_populate_smc_initial_state()
4918 	table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;  in si_populate_smc_initial_state()
4955 	struct si_power_info *si_pi = si_get_pi(adev);  in si_populate_smc_acpi_state()  local
4956 	u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;  in si_populate_smc_acpi_state()
4957 	u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;  in si_populate_smc_acpi_state()
4958 	u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;  in si_populate_smc_acpi_state()
4959 	u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;  in si_populate_smc_acpi_state()
4960 	u32 dll_cntl = si_pi->clock_registers.dll_cntl;  in si_populate_smc_acpi_state()
4961 	u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;  in si_populate_smc_acpi_state()
4962 	u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;  in si_populate_smc_acpi_state()
4963 	u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;  in si_populate_smc_acpi_state()
4964 	u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;  in si_populate_smc_acpi_state()
4965 	u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;  in si_populate_smc_acpi_state()
4966 	u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;  in si_populate_smc_acpi_state()
4987 		table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;  in si_populate_smc_acpi_state()
4989 		if (si_pi->vddc_phase_shed_control) {  in si_populate_smc_acpi_state()
5013 							si_pi->sys_pcie_mask,  in si_populate_smc_acpi_state()
5014 							si_pi->boot_pcie_gen,  in si_populate_smc_acpi_state()
5017 		if (si_pi->vddc_phase_shed_control)  in si_populate_smc_acpi_state()
5056 		cpu_to_be32(si_pi->clock_registers.mpll_ss1);  in si_populate_smc_acpi_state()
5058 		cpu_to_be32(si_pi->clock_registers.mpll_ss2);  in si_populate_smc_acpi_state()
5096 	struct si_power_info *si_pi = si_get_pi(adev);  in si_populate_ulv_state()  local
5097 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_populate_ulv_state()
5125 	struct si_power_info *si_pi = si_get_pi(adev);  in si_program_ulv_memory_timing_parameters()  local
5126 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_program_ulv_memory_timing_parameters()
5139 					  si_pi->arb_table_start +  in si_program_ulv_memory_timing_parameters()
5144 					  si_pi->sram_end);  in si_program_ulv_memory_timing_parameters()
5158 	struct si_power_info *si_pi = si_get_pi(adev);  in si_init_smc_table()  local
5160 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_init_smc_table()
5161 	SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;  in si_init_smc_table()
5238 	return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,  in si_init_smc_table()
5240 					   si_pi->sram_end);  in si_init_smc_table()
5248 	struct si_power_info *si_pi = si_get_pi(adev);  in si_calculate_sclk_params()  local
5250 	u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;  in si_calculate_sclk_params()
5251 	u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;  in si_calculate_sclk_params()
5252 	u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;  in si_calculate_sclk_params()
5253 	u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;  in si_calculate_sclk_params()
5254 	u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;  in si_calculate_sclk_params()
5255 	u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;  in si_calculate_sclk_params()
5342 	struct si_power_info *si_pi = si_get_pi(adev);  in si_populate_mclk_value()  local
5343 	u32  dll_cntl = si_pi->clock_registers.dll_cntl;  in si_populate_mclk_value()
5344 	u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;  in si_populate_mclk_value()
5345 	u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;  in si_populate_mclk_value()
5346 	u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;  in si_populate_mclk_value()
5347 	u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;  in si_populate_mclk_value()
5348 	u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;  in si_populate_mclk_value()
5349 	u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;  in si_populate_mclk_value()
5350 	u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;  in si_populate_mclk_value()
5351 	u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;  in si_populate_mclk_value()
5444 	struct si_power_info *si_pi = si_get_pi(adev);  in si_convert_power_level_to_smc()  local
5451 	    (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))  in si_convert_power_level_to_smc()
5452 		level->gen2PCIE = (u8)si_pi->force_pcie_gen;  in si_convert_power_level_to_smc()
5529 	if (si_pi->vddc_phase_shed_control) {  in si_convert_power_level_to_smc()
5540 	level->MaxPoweredUpCU = si_pi->max_cu;  in si_convert_power_level_to_smc()
5598 	struct si_power_info *si_pi = si_get_pi(adev);  in si_disable_ulv()  local
5599 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_disable_ulv()
5611 	const struct si_power_info *si_pi = si_get_pi(adev);  in si_is_state_ulv_compatible()  local
5612 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_is_state_ulv_compatible()
5639 	const struct si_power_info *si_pi = si_get_pi(adev);  in si_set_power_state_conditionally_enable_ulv()  local
5640 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_set_power_state_conditionally_enable_ulv()
5656 	struct si_power_info *si_pi = si_get_pi(adev);  in si_convert_power_state_to_smc()  local
5681 			if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {  in si_convert_power_state_to_smc()
5733 	struct si_power_info *si_pi = si_get_pi(adev);  in si_upload_sw_state()  local
5736 	u32 address = si_pi->state_table_start +  in si_upload_sw_state()
5741 	SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;  in si_upload_sw_state()
5750 					   state_size, si_pi->sram_end);  in si_upload_sw_state()
5755 	struct si_power_info *si_pi = si_get_pi(adev);  in si_upload_ulv_state()  local
5756 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_upload_ulv_state()
5760 		u32 address = si_pi->state_table_start +  in si_upload_ulv_state()
5762 		SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;  in si_upload_ulv_state()
5770 							  state_size, si_pi->sram_end);  in si_upload_ulv_state()
5988 	struct si_power_info *si_pi = si_get_pi(adev);  in si_initialize_mc_reg_table()  local
5990 	struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;  in si_initialize_mc_reg_table()
6039 	struct si_power_info *si_pi = si_get_pi(adev);  in si_populate_mc_reg_addresses()  local
6042 	for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {  in si_populate_mc_reg_addresses()
6043 		if (si_pi->mc_reg_table.valid_flag & (1 << j)) {  in si_populate_mc_reg_addresses()
6047 				cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);  in si_populate_mc_reg_addresses()
6049 				cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);  in si_populate_mc_reg_addresses()
6074 	struct si_power_info *si_pi = si_get_pi(adev);  in si_convert_mc_reg_table_entry_to_smc()  local
6077 	for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {  in si_convert_mc_reg_table_entry_to_smc()
6078 		if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)  in si_convert_mc_reg_table_entry_to_smc()
6082 	if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))  in si_convert_mc_reg_table_entry_to_smc()
6085 	si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],  in si_convert_mc_reg_table_entry_to_smc()
6086 				mc_reg_table_data, si_pi->mc_reg_table.last,  in si_convert_mc_reg_table_entry_to_smc()
6087 				si_pi->mc_reg_table.valid_flag);  in si_convert_mc_reg_table_entry_to_smc()
6108 	struct si_power_info *si_pi = si_get_pi(adev);  in si_populate_mc_reg_table()  local
6109 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_populate_mc_reg_table()
6110 	SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;  in si_populate_mc_reg_table()
6121 	si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],  in si_populate_mc_reg_table()
6123 				si_pi->mc_reg_table.last,  in si_populate_mc_reg_table()
6124 				si_pi->mc_reg_table.valid_flag);  in si_populate_mc_reg_table()
6130 		si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],  in si_populate_mc_reg_table()
6132 					si_pi->mc_reg_table.last,  in si_populate_mc_reg_table()
6133 					si_pi->mc_reg_table.valid_flag);  in si_populate_mc_reg_table()
6137 	return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,  in si_populate_mc_reg_table()
6139 					   sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);  in si_populate_mc_reg_table()
6146 	struct si_power_info *si_pi = si_get_pi(adev);  in si_upload_mc_reg_table()  local
6147 	u32 address = si_pi->mc_reg_table_start +  in si_upload_mc_reg_table()
6150 	SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;  in si_upload_mc_reg_table()
6159 					   si_pi->sram_end);  in si_upload_mc_reg_table()
6199 	struct si_power_info *si_pi = si_get_pi(adev);  in si_request_link_speed_change_before_state_change()  local
6203 	if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)  in si_request_link_speed_change_before_state_change()
6206 		current_link_speed = si_pi->force_pcie_gen;  in si_request_link_speed_change_before_state_change()
6208 	si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;  in si_request_link_speed_change_before_state_change()
6209 	si_pi->pspp_notify_required = false;  in si_request_link_speed_change_before_state_change()
6216 			si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;  in si_request_link_speed_change_before_state_change()
6224 			si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);  in si_request_link_speed_change_before_state_change()
6229 			si_pi->pspp_notify_required = true;  in si_request_link_speed_change_before_state_change()
6237 	struct si_power_info *si_pi = si_get_pi(adev);  in si_notify_link_speed_change_after_state_change()  local
6241 	if (si_pi->pspp_notify_required) {  in si_notify_link_speed_change_after_state_change()
6280 	struct si_power_info *si_pi = si_get_pi(adev);  in si_set_max_cu_value()  local
6289 			si_pi->max_cu = 10;  in si_set_max_cu_value()
6295 			si_pi->max_cu = 8;  in si_set_max_cu_value()
6303 			si_pi->max_cu = 10;  in si_set_max_cu_value()
6308 			si_pi->max_cu = 8;  in si_set_max_cu_value()
6311 			si_pi->max_cu = 0;  in si_set_max_cu_value()
6315 		si_pi->max_cu = 0;  in si_set_max_cu_value()
6442 	struct si_power_info *si_pi = si_get_pi(adev);  in si_fan_ctrl_set_static_mode()  local
6445 	if (si_pi->fan_ctrl_is_in_default_mode) {  in si_fan_ctrl_set_static_mode()
6447 		si_pi->fan_ctrl_default_mode = tmp;  in si_fan_ctrl_set_static_mode()
6449 		si_pi->t_min = tmp;  in si_fan_ctrl_set_static_mode()
6450 		si_pi->fan_ctrl_is_in_default_mode = false;  in si_fan_ctrl_set_static_mode()
6464 	struct si_power_info *si_pi = si_get_pi(adev);  in si_thermal_setup_fan_table()  local
6473 	if (!si_pi->fan_table_start) {  in si_thermal_setup_fan_table()
6518 					  si_pi->fan_table_start,  in si_thermal_setup_fan_table()
6521 					  si_pi->sram_end);  in si_thermal_setup_fan_table()
6533 	struct si_power_info *si_pi = si_get_pi(adev);  in si_fan_ctrl_start_smc_fan_control()  local
6538 		si_pi->fan_is_controlled_by_smc = true;  in si_fan_ctrl_start_smc_fan_control()
6547 	struct si_power_info *si_pi = si_get_pi(adev);  in si_fan_ctrl_stop_smc_fan_control()  local
6553 		si_pi->fan_is_controlled_by_smc = false;  in si_fan_ctrl_stop_smc_fan_control()
6590 	struct si_power_info *si_pi = si_get_pi(adev);  in si_dpm_set_fan_speed_percent()  local
6598 	if (si_pi->fan_is_controlled_by_smc)  in si_dpm_set_fan_speed_percent()
6641 	struct si_power_info *si_pi = si_get_pi(adev);  in si_dpm_get_fan_control_mode()  local
6644 	if (si_pi->fan_is_controlled_by_smc)  in si_dpm_get_fan_control_mode()
6705 	struct si_power_info *si_pi = si_get_pi(adev);  in si_fan_ctrl_set_default_mode()  local
6708 	if (!si_pi->fan_ctrl_is_in_default_mode) {  in si_fan_ctrl_set_default_mode()
6710 		tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);  in si_fan_ctrl_set_default_mode()
6714 		tmp |= TMIN(si_pi->t_min);  in si_fan_ctrl_set_default_mode()
6716 		si_pi->fan_ctrl_is_in_default_mode = true;  in si_fan_ctrl_set_default_mode()
6782 	struct si_power_info *si_pi = si_get_pi(adev);  in si_dpm_enable()  local
6788 	if (pi->voltage_control || si_pi->voltage_control_svi2)  in si_dpm_enable()
6792 	if (pi->voltage_control || si_pi->voltage_control_svi2) {  in si_dpm_enable()
7135 	struct si_power_info *si_pi = si_get_pi(adev);  in si_parse_pplib_clock_info()  local
7152 						   si_pi->sys_pcie_mask,  in si_parse_pplib_clock_info()
7153 						   si_pi->boot_pcie_gen,  in si_parse_pplib_clock_info()
7165 		si_pi->acpi_pcie_gen = pl->pcie_gen;  in si_parse_pplib_clock_info()
7171 		si_pi->ulv.supported = false;  in si_parse_pplib_clock_info()
7172 		si_pi->ulv.pl = *pl;  in si_parse_pplib_clock_info()
7173 		si_pi->ulv.one_pcie_lane_in_ulv = false;  in si_parse_pplib_clock_info()
7174 		si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;  in si_parse_pplib_clock_info()
7175 		si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;  in si_parse_pplib_clock_info()
7176 		si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;  in si_parse_pplib_clock_info()
7193 		si_pi->mvdd_bootup_value = mvdd;  in si_parse_pplib_clock_info()
7307 	struct si_power_info *si_pi;  in si_dpm_init()  local
7311 	si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);  in si_dpm_init()
7312 	if (si_pi == NULL)  in si_dpm_init()
7314 	adev->pm.dpm.priv = si_pi;  in si_dpm_init()
7315 	ni_pi = &si_pi->ni;  in si_dpm_init()
7319 	si_pi->sys_pcie_mask =  in si_dpm_init()
7321 	si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;  in si_dpm_init()
7322 	si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);  in si_dpm_init()
7393 		si_pi->voltage_control_svi2 =  in si_dpm_init()
7396 		if (si_pi->voltage_control_svi2)  in si_dpm_init()
7398 						  &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);  in si_dpm_init()
7409 		si_pi->vddci_control_svi2 =  in si_dpm_init()
7413 	si_pi->vddc_phase_shed_control =  in si_dpm_init()
7426 	si_pi->sclk_deep_sleep_above_low = false;  in si_dpm_init()
7443 	si_pi->sram_end = SMC_RAM_END;  in si_dpm_init()
7461 	si_pi->fan_ctrl_is_in_default_mode = true;  in si_dpm_init()