Lines Matching refs:pl
1845 struct rv7xx_pl *pl,
3287 struct rv7xx_pl *pl) in btc_adjust_clock_combinations() argument
3290 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations()
3293 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations()
3296 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations()
3297 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
3298 pl->sclk = btc_get_valid_sclk(adev, in btc_adjust_clock_combinations()
3300 (pl->mclk + in btc_adjust_clock_combinations()
3304 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
3305 pl->mclk = btc_get_valid_mclk(adev, in btc_adjust_clock_combinations()
3307 pl->sclk - in btc_adjust_clock_combinations()
4757 struct rv7xx_pl *pl, in si_populate_memory_timing_parameters() argument
4765 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk); in si_populate_memory_timing_parameters()
4768 pl->sclk, in si_populate_memory_timing_parameters()
4769 pl->mclk); in si_populate_memory_timing_parameters()
5101 ret = si_convert_power_level_to_smc(adev, &ulv->pl, in si_populate_ulv_state()
5130 ret = si_populate_memory_timing_parameters(adev, &ulv->pl, in si_program_ulv_memory_timing_parameters()
5220 if (ulv->supported && ulv->pl.vddc) { in si_init_smc_table()
5439 struct rv7xx_pl *pl, in si_convert_power_level_to_smc() argument
5454 level->gen2PCIE = (u8)pl->pcie_gen; in si_convert_power_level_to_smc()
5456 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk); in si_convert_power_level_to_smc()
5463 (pl->mclk <= pi->mclk_stutter_mode_threshold) && in si_convert_power_level_to_smc()
5474 if (pl->mclk > pi->mclk_edc_enable_threshold) in si_convert_power_level_to_smc()
5477 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) in si_convert_power_level_to_smc()
5480 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk); in si_convert_power_level_to_smc()
5483 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= in si_convert_power_level_to_smc()
5493 pl->mclk); in si_convert_power_level_to_smc()
5499 pl->sclk, in si_convert_power_level_to_smc()
5500 pl->mclk, in si_convert_power_level_to_smc()
5508 pl->vddc, &level->vddc); in si_convert_power_level_to_smc()
5524 pl->vddci, &level->vddci); in si_convert_power_level_to_smc()
5532 pl->vddc, in si_convert_power_level_to_smc()
5533 pl->sclk, in si_convert_power_level_to_smc()
5534 pl->mclk, in si_convert_power_level_to_smc()
5542 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd); in si_convert_power_level_to_smc()
5616 if (state->performance_levels[0].mclk != ulv->pl.mclk) in si_is_state_ulv_compatible()
5624 if (ulv->pl.vddc < in si_is_state_ulv_compatible()
5759 if (ulv->supported && ulv->pl.vddc) { in si_upload_ulv_state()
6071 struct rv7xx_pl *pl, in si_convert_mc_reg_table_entry_to_smc() argument
6078 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in si_convert_mc_reg_table_entry_to_smc()
6126 if (ulv->supported && ulv->pl.vddc != 0) in si_populate_mc_reg_table()
6127 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl, in si_populate_mc_reg_table()
7138 struct rv7xx_pl *pl = &ps->performance_levels[index]; in si_parse_pplib_clock_info() local
7143 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); in si_parse_pplib_clock_info()
7144 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; in si_parse_pplib_clock_info()
7145 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); in si_parse_pplib_clock_info()
7146 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; in si_parse_pplib_clock_info()
7148 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); in si_parse_pplib_clock_info()
7149 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); in si_parse_pplib_clock_info()
7150 pl->flags = le32_to_cpu(clock_info->si.ulFlags); in si_parse_pplib_clock_info()
7151 pl->pcie_gen = amdgpu_get_pcie_gen_support(adev, in si_parse_pplib_clock_info()
7157 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc, in si_parse_pplib_clock_info()
7160 pl->vddc = leakage_voltage; in si_parse_pplib_clock_info()
7163 pi->acpi_vddc = pl->vddc; in si_parse_pplib_clock_info()
7164 eg_pi->acpi_vddci = pl->vddci; in si_parse_pplib_clock_info()
7165 si_pi->acpi_pcie_gen = pl->pcie_gen; in si_parse_pplib_clock_info()
7172 si_pi->ulv.pl = *pl; in si_parse_pplib_clock_info()
7179 if (pi->min_vddc_in_table > pl->vddc) in si_parse_pplib_clock_info()
7180 pi->min_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
7182 if (pi->max_vddc_in_table < pl->vddc) in si_parse_pplib_clock_info()
7183 pi->max_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
7189 pl->mclk = adev->clock.default_mclk; in si_parse_pplib_clock_info()
7190 pl->sclk = adev->clock.default_sclk; in si_parse_pplib_clock_info()
7191 pl->vddc = vddc; in si_parse_pplib_clock_info()
7192 pl->vddci = vddci; in si_parse_pplib_clock_info()
7198 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in si_parse_pplib_clock_info()
7199 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in si_parse_pplib_clock_info()
7200 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in si_parse_pplib_clock_info()
7201 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in si_parse_pplib_clock_info()
7486 struct rv7xx_pl *pl; in si_dpm_debugfs_print_current_performance_level() local
7494 pl = &ps->performance_levels[current_index]; in si_dpm_debugfs_print_current_performance_level()
7497 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_debugfs_print_current_performance_level()
7897 struct rv7xx_pl *pl; in si_dpm_print_power_state() local
7904 pl = &ps->performance_levels[i]; in si_dpm_print_power_state()
7907 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_print_power_state()
7910 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci); in si_dpm_print_power_state()