64 				struct amdgpu_ib *ib,  in si_dma_ring_emit_ib()  argument
73 	amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));  in si_dma_ring_emit_ib()
74 	amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));  in si_dma_ring_emit_ib()
264 	struct amdgpu_ib ib;  in si_dma_ring_test_ib()  local
280 	memset(&ib, 0, sizeof(ib));  in si_dma_ring_test_ib()
281 	r = amdgpu_ib_get(adev, NULL, 256, &ib);  in si_dma_ring_test_ib()
287 	ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, 1);  in si_dma_ring_test_ib()
288 	ib.ptr[1] = lower_32_bits(gpu_addr);  in si_dma_ring_test_ib()
289 	ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff;  in si_dma_ring_test_ib()
290 	ib.ptr[3] = 0xDEADBEEF;  in si_dma_ring_test_ib()
291 	ib.length_dw = 4;  in si_dma_ring_test_ib()
292 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);  in si_dma_ring_test_ib()
315 	amdgpu_ib_free(adev, &ib, NULL);  in si_dma_ring_test_ib()
332 static void si_dma_vm_copy_pte(struct amdgpu_ib *ib,  in si_dma_vm_copy_pte()  argument
338 	ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY,  in si_dma_vm_copy_pte()
340 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);  in si_dma_vm_copy_pte()
341 	ib->ptr[ib->length_dw++] = lower_32_bits(src);  in si_dma_vm_copy_pte()
342 	ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;  in si_dma_vm_copy_pte()
343 	ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff;  in si_dma_vm_copy_pte()
357 static void si_dma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,  in si_dma_vm_write_pte()  argument
363 	ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw);  in si_dma_vm_write_pte()
364 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);  in si_dma_vm_write_pte()
365 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);  in si_dma_vm_write_pte()
367 		ib->ptr[ib->length_dw++] = lower_32_bits(value);  in si_dma_vm_write_pte()
368 		ib->ptr[ib->length_dw++] = upper_32_bits(value);  in si_dma_vm_write_pte()
385 static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib,  in si_dma_vm_set_pte_pde()  argument
404 		ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);  in si_dma_vm_set_pte_pde()
405 		ib->ptr[ib->length_dw++] = pe; /* dst addr */  in si_dma_vm_set_pte_pde()
406 		ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;  in si_dma_vm_set_pte_pde()
407 		ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */  in si_dma_vm_set_pte_pde()
408 		ib->ptr[ib->length_dw++] = upper_32_bits(flags);  in si_dma_vm_set_pte_pde()
409 		ib->ptr[ib->length_dw++] = value; /* value */  in si_dma_vm_set_pte_pde()
410 		ib->ptr[ib->length_dw++] = upper_32_bits(value);  in si_dma_vm_set_pte_pde()
411 		ib->ptr[ib->length_dw++] = incr; /* increment size */  in si_dma_vm_set_pte_pde()
412 		ib->ptr[ib->length_dw++] = 0;  in si_dma_vm_set_pte_pde()
425 static void si_dma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)  in si_dma_ring_pad_ib()  argument
427 	while (ib->length_dw & 0x7)  in si_dma_ring_pad_ib()
428 		ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0);  in si_dma_ring_pad_ib()
818 static void si_dma_emit_copy_buffer(struct amdgpu_ib *ib,  in si_dma_emit_copy_buffer()  argument
823 	ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY,  in si_dma_emit_copy_buffer()
825 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);  in si_dma_emit_copy_buffer()
826 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);  in si_dma_emit_copy_buffer()
827 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) & 0xff;  in si_dma_emit_copy_buffer()
828 	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset) & 0xff;  in si_dma_emit_copy_buffer()
841 static void si_dma_emit_fill_buffer(struct amdgpu_ib *ib,  in si_dma_emit_fill_buffer()  argument
846 	ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_CONSTANT_FILL,  in si_dma_emit_fill_buffer()
848 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);  in si_dma_emit_fill_buffer()
849 	ib->ptr[ib->length_dw++] = src_data;  in si_dma_emit_fill_buffer()
850 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) << 16;  in si_dma_emit_fill_buffer()