230 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v4_0_init_microcode()
235 		err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);  in sdma_v4_0_init_microcode()
238 		err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);  in sdma_v4_0_init_microcode()
241 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;  in sdma_v4_0_init_microcode()
242 		adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);  in sdma_v4_0_init_microcode()
243 		adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);  in sdma_v4_0_init_microcode()
244 		if (adev->sdma.instance[i].feature_version >= 20)  in sdma_v4_0_init_microcode()
245 			adev->sdma.instance[i].burst_nop = true;  in sdma_v4_0_init_microcode()
252 			info->fw = adev->sdma.instance[i].fw;  in sdma_v4_0_init_microcode()
261 		for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v4_0_init_microcode()
262 			release_firmware(adev->sdma.instance[i].fw);  in sdma_v4_0_init_microcode()
263 			adev->sdma.instance[i].fw = NULL;  in sdma_v4_0_init_microcode()
361 	struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);  in sdma_v4_0_ring_insert_nop()  local
365 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v4_0_ring_insert_nop()
495 	struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;  in sdma_v4_0_gfx_stop()
496 	struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;  in sdma_v4_0_gfx_stop()
504 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v4_0_gfx_stop()
566 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v4_0_ctx_switch_enable()
601 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v4_0_enable()
628 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v4_0_gfx_resume()
629 		ring = &adev->sdma.instance[i].ring;  in sdma_v4_0_gfx_resume()
847 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v4_0_load_microcode()
848 		if (!adev->sdma.instance[i].fw)  in sdma_v4_0_load_microcode()
851 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;  in sdma_v4_0_load_microcode()
856 			(adev->sdma.instance[i].fw->data +  in sdma_v4_0_load_microcode()
864 		WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);  in sdma_v4_0_load_microcode()
1143 	struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);  in sdma_v4_0_ring_pad_ib()  local
1149 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v4_0_ring_pad_ib()
1214 		adev->sdma.num_instances = 1;  in sdma_v4_0_early_init()
1216 		adev->sdma.num_instances = 2;  in sdma_v4_0_early_init()
1235 			      &adev->sdma.trap_irq);  in sdma_v4_0_sw_init()
1241 			      &adev->sdma.trap_irq);  in sdma_v4_0_sw_init()
1251 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v4_0_sw_init()
1252 		ring = &adev->sdma.instance[i].ring;  in sdma_v4_0_sw_init()
1265 				     &adev->sdma.trap_irq,  in sdma_v4_0_sw_init()
1281 	for (i = 0; i < adev->sdma.num_instances; i++)  in sdma_v4_0_sw_fini()
1282 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);  in sdma_v4_0_sw_fini()
1284 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v4_0_sw_fini()
1285 		release_firmware(adev->sdma.instance[i].fw);  in sdma_v4_0_sw_fini()
1286 		adev->sdma.instance[i].fw = NULL;  in sdma_v4_0_sw_fini()
1336 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v4_0_is_idle()
1398 			amdgpu_fence_process(&adev->sdma.instance[0].ring);  in sdma_v4_0_process_trap_irq()
1414 			amdgpu_fence_process(&adev->sdma.instance[1].ring);  in sdma_v4_0_process_trap_irq()
1461 		if (adev->sdma.num_instances > 1) {  in sdma_v4_0_update_medium_grain_clock_gating()
1489 		if (adev->sdma.num_instances > 1) {  in sdma_v4_0_update_medium_grain_clock_gating()
1520 		if (adev->sdma.num_instances > 1) {  in sdma_v4_0_update_medium_grain_light_sleep()
1534 		if (adev->sdma.num_instances > 1) {  in sdma_v4_0_update_medium_grain_light_sleep()
1657 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v4_0_set_ring_funcs()
1658 		adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;  in sdma_v4_0_set_ring_funcs()
1659 		adev->sdma.instance[i].ring.me = i;  in sdma_v4_0_set_ring_funcs()
1674 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;  in sdma_v4_0_set_irq_funcs()
1675 	adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;  in sdma_v4_0_set_irq_funcs()
1676 	adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;  in sdma_v4_0_set_irq_funcs()
1742 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;  in sdma_v4_0_set_buffer_funcs()
1760 		for (i = 0; i < adev->sdma.num_instances; i++)  in sdma_v4_0_set_vm_pte_funcs()
1762 				&adev->sdma.instance[i].ring;  in sdma_v4_0_set_vm_pte_funcs()
1764 		adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;  in sdma_v4_0_set_vm_pte_funcs()