Lines Matching refs:pi
380 struct kv_power_info *pi = adev->pm.dpm.priv; in kv_get_pi() local
382 return pi; in kv_get_pi()
462 struct kv_power_info *pi = kv_get_pi(adev); in kv_do_enable_didt() local
465 if (pi->caps_sq_ramping) { in kv_do_enable_didt()
474 if (pi->caps_db_ramping) { in kv_do_enable_didt()
483 if (pi->caps_td_ramping) { in kv_do_enable_didt()
492 if (pi->caps_tcp_ramping) { in kv_do_enable_didt()
504 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_didt() local
507 if (pi->caps_sq_ramping || in kv_enable_didt()
508 pi->caps_db_ramping || in kv_enable_didt()
509 pi->caps_td_ramping || in kv_enable_didt()
510 pi->caps_tcp_ramping) { in kv_enable_didt()
532 struct kv_power_info *pi = kv_get_pi(adev);
534 if (pi->caps_cac) {
564 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_smc_cac() local
567 if (pi->caps_cac) { in kv_enable_smc_cac()
571 pi->cac_enabled = false; in kv_enable_smc_cac()
573 pi->cac_enabled = true; in kv_enable_smc_cac()
574 } else if (pi->cac_enabled) { in kv_enable_smc_cac()
576 pi->cac_enabled = false; in kv_enable_smc_cac()
585 struct kv_power_info *pi = kv_get_pi(adev); in kv_process_firmware_header() local
591 &tmp, pi->sram_end); in kv_process_firmware_header()
594 pi->dpm_table_start = tmp; in kv_process_firmware_header()
598 &tmp, pi->sram_end); in kv_process_firmware_header()
601 pi->soft_regs_start = tmp; in kv_process_firmware_header()
608 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_dpm_voltage_scaling() local
611 pi->graphics_voltage_change_enable = 1; in kv_enable_dpm_voltage_scaling()
614 pi->dpm_table_start + in kv_enable_dpm_voltage_scaling()
616 &pi->graphics_voltage_change_enable, in kv_enable_dpm_voltage_scaling()
617 sizeof(u8), pi->sram_end); in kv_enable_dpm_voltage_scaling()
624 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_interval() local
627 pi->graphics_interval = 1; in kv_set_dpm_interval()
630 pi->dpm_table_start + in kv_set_dpm_interval()
632 &pi->graphics_interval, in kv_set_dpm_interval()
633 sizeof(u8), pi->sram_end); in kv_set_dpm_interval()
640 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_boot_state() local
644 pi->dpm_table_start + in kv_set_dpm_boot_state()
646 &pi->graphics_boot_level, in kv_set_dpm_boot_state()
647 sizeof(u8), pi->sram_end); in kv_set_dpm_boot_state()
665 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_divider_value() local
674 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
675 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
689 struct kv_power_info *pi = kv_get_pi(adev); in kv_convert_2bit_index_to_voltage() local
691 &pi->sys_info.vid_mapping_table, in kv_convert_2bit_index_to_voltage()
700 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_vid() local
702 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; in kv_set_vid()
703 pi->graphics_level[index].MinVddNb = in kv_set_vid()
711 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_at() local
713 pi->graphics_level[index].AT = cpu_to_be16((u16)at); in kv_set_at()
721 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enable() local
723 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; in kv_dpm_power_level_enable()
783 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_sclk_t() local
787 if (pi->caps_sclk_throttle_low_notification) { in kv_update_sclk_t()
788 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in kv_update_sclk_t()
791 pi->dpm_table_start + in kv_update_sclk_t()
794 sizeof(u32), pi->sram_end); in kv_update_sclk_t()
801 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_bootup_state() local
807 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
808 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
812 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
816 &pi->sys_info.sclk_voltage_mapping_table; in kv_program_bootup_state()
821 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
822 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
826 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
834 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_auto_thermal_throttling() local
837 pi->graphics_therm_throttle_enable = 1; in kv_enable_auto_thermal_throttling()
840 pi->dpm_table_start + in kv_enable_auto_thermal_throttling()
842 &pi->graphics_therm_throttle_enable, in kv_enable_auto_thermal_throttling()
843 sizeof(u8), pi->sram_end); in kv_enable_auto_thermal_throttling()
850 struct kv_power_info *pi = kv_get_pi(adev); in kv_upload_dpm_settings() local
854 pi->dpm_table_start + in kv_upload_dpm_settings()
856 (u8 *)&pi->graphics_level, in kv_upload_dpm_settings()
858 pi->sram_end); in kv_upload_dpm_settings()
864 pi->dpm_table_start + in kv_upload_dpm_settings()
866 &pi->graphics_dpm_level_count, in kv_upload_dpm_settings()
867 sizeof(u8), pi->sram_end); in kv_upload_dpm_settings()
879 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_clk_bypass() local
882 if (pi->caps_enable_dfs_bypass) { in kv_get_clk_bypass()
904 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_uvd_table() local
914 pi->uvd_level_count = 0; in kv_populate_uvd_table()
916 if (pi->high_voltage_t && in kv_populate_uvd_table()
917 (pi->high_voltage_t < table->entries[i].v)) in kv_populate_uvd_table()
920 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
921 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); in kv_populate_uvd_table()
922 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); in kv_populate_uvd_table()
924 pi->uvd_level[i].VClkBypassCntl = in kv_populate_uvd_table()
926 pi->uvd_level[i].DClkBypassCntl = in kv_populate_uvd_table()
933 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
939 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
941 pi->uvd_level_count++; in kv_populate_uvd_table()
945 pi->dpm_table_start + in kv_populate_uvd_table()
947 (u8 *)&pi->uvd_level_count, in kv_populate_uvd_table()
948 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
952 pi->uvd_interval = 1; in kv_populate_uvd_table()
955 pi->dpm_table_start + in kv_populate_uvd_table()
957 &pi->uvd_interval, in kv_populate_uvd_table()
958 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
963 pi->dpm_table_start + in kv_populate_uvd_table()
965 (u8 *)&pi->uvd_level, in kv_populate_uvd_table()
967 pi->sram_end); in kv_populate_uvd_table()
975 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_vce_table() local
985 pi->vce_level_count = 0; in kv_populate_vce_table()
987 if (pi->high_voltage_t && in kv_populate_vce_table()
988 pi->high_voltage_t < table->entries[i].v) in kv_populate_vce_table()
991 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); in kv_populate_vce_table()
992 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_vce_table()
994 pi->vce_level[i].ClkBypassCntl = in kv_populate_vce_table()
1001 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()
1003 pi->vce_level_count++; in kv_populate_vce_table()
1007 pi->dpm_table_start + in kv_populate_vce_table()
1009 (u8 *)&pi->vce_level_count, in kv_populate_vce_table()
1011 pi->sram_end); in kv_populate_vce_table()
1015 pi->vce_interval = 1; in kv_populate_vce_table()
1018 pi->dpm_table_start + in kv_populate_vce_table()
1020 (u8 *)&pi->vce_interval, in kv_populate_vce_table()
1022 pi->sram_end); in kv_populate_vce_table()
1027 pi->dpm_table_start + in kv_populate_vce_table()
1029 (u8 *)&pi->vce_level, in kv_populate_vce_table()
1031 pi->sram_end); in kv_populate_vce_table()
1038 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_samu_table() local
1048 pi->samu_level_count = 0; in kv_populate_samu_table()
1050 if (pi->high_voltage_t && in kv_populate_samu_table()
1051 pi->high_voltage_t < table->entries[i].v) in kv_populate_samu_table()
1054 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_samu_table()
1055 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_samu_table()
1057 pi->samu_level[i].ClkBypassCntl = in kv_populate_samu_table()
1064 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()
1066 pi->samu_level_count++; in kv_populate_samu_table()
1070 pi->dpm_table_start + in kv_populate_samu_table()
1072 (u8 *)&pi->samu_level_count, in kv_populate_samu_table()
1074 pi->sram_end); in kv_populate_samu_table()
1078 pi->samu_interval = 1; in kv_populate_samu_table()
1081 pi->dpm_table_start + in kv_populate_samu_table()
1083 (u8 *)&pi->samu_interval, in kv_populate_samu_table()
1085 pi->sram_end); in kv_populate_samu_table()
1090 pi->dpm_table_start + in kv_populate_samu_table()
1092 (u8 *)&pi->samu_level, in kv_populate_samu_table()
1094 pi->sram_end); in kv_populate_samu_table()
1104 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_acp_table() local
1114 pi->acp_level_count = 0; in kv_populate_acp_table()
1116 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_acp_table()
1117 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_acp_table()
1123 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
1125 pi->acp_level_count++; in kv_populate_acp_table()
1129 pi->dpm_table_start + in kv_populate_acp_table()
1131 (u8 *)&pi->acp_level_count, in kv_populate_acp_table()
1133 pi->sram_end); in kv_populate_acp_table()
1137 pi->acp_interval = 1; in kv_populate_acp_table()
1140 pi->dpm_table_start + in kv_populate_acp_table()
1142 (u8 *)&pi->acp_interval, in kv_populate_acp_table()
1144 pi->sram_end); in kv_populate_acp_table()
1149 pi->dpm_table_start + in kv_populate_acp_table()
1151 (u8 *)&pi->acp_level, in kv_populate_acp_table()
1153 pi->sram_end); in kv_populate_acp_table()
1162 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dfs_bypass_settings() local
1168 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
1169 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
1171 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
1173 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
1175 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
1177 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
1179 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
1181 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1183 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1188 &pi->sys_info.sclk_voltage_mapping_table; in kv_calculate_dfs_bypass_settings()
1189 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
1190 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
1192 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
1194 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
1196 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
1198 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
1200 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
1202 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1204 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1218 struct kv_power_info *pi = kv_get_pi(adev); in kv_reset_acp_boot_level() local
1220 pi->acp_boot_level = 0xff; in kv_reset_acp_boot_level()
1227 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_current_ps() local
1229 pi->current_rps = *rps; in kv_update_current_ps()
1230 pi->current_ps = *new_ps; in kv_update_current_ps()
1231 pi->current_rps.ps_priv = &pi->current_ps; in kv_update_current_ps()
1232 adev->pm.dpm.current_ps = &pi->current_rps; in kv_update_current_ps()
1239 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_requested_ps() local
1241 pi->requested_rps = *rps; in kv_update_requested_ps()
1242 pi->requested_ps = *new_ps; in kv_update_requested_ps()
1243 pi->requested_rps.ps_priv = &pi->requested_ps; in kv_update_requested_ps()
1244 adev->pm.dpm.requested_ps = &pi->requested_rps; in kv_update_requested_ps()
1250 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable_bapm() local
1253 if (pi->bapm_enable) { in kv_dpm_enable_bapm()
1262 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable() local
1308 if (pi->enable_auto_thermal_throttling) { in kv_dpm_enable()
1373 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_disable() local
1388 if (pi->caps_vce_pg) /* power on the VCE block */ in kv_dpm_disable()
1390 if (pi->caps_uvd_pg) /* power on the UVD block */ in kv_dpm_disable()
1407 struct kv_power_info *pi = kv_get_pi(adev);
1409 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1410 (u8 *)&value, sizeof(u16), pi->sram_end);
1416 struct kv_power_info *pi = kv_get_pi(adev);
1418 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
1419 value, pi->sram_end);
1425 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_sclk_t() local
1427 pi->low_sclk_interrupt_t = 0; in kv_init_sclk_t()
1432 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_fps_limits() local
1435 if (pi->caps_fps) { in kv_init_fps_limits()
1439 pi->fps_high_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1441 pi->dpm_table_start + in kv_init_fps_limits()
1443 (u8 *)&pi->fps_high_t, in kv_init_fps_limits()
1444 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1447 pi->fps_low_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1450 pi->dpm_table_start + in kv_init_fps_limits()
1452 (u8 *)&pi->fps_low_t, in kv_init_fps_limits()
1453 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1461 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_powergate_state() local
1463 pi->uvd_power_gated = false; in kv_init_powergate_state()
1464 pi->vce_power_gated = false; in kv_init_powergate_state()
1465 pi->samu_power_gated = false; in kv_init_powergate_state()
1466 pi->acp_power_gated = false; in kv_init_powergate_state()
1496 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_uvd_dpm() local
1504 pi->uvd_boot_level = table->count - 1; in kv_update_uvd_dpm()
1506 pi->uvd_boot_level = 0; in kv_update_uvd_dpm()
1508 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) { in kv_update_uvd_dpm()
1509 mask = 1 << pi->uvd_boot_level; in kv_update_uvd_dpm()
1515 pi->dpm_table_start + in kv_update_uvd_dpm()
1517 (uint8_t *)&pi->uvd_boot_level, in kv_update_uvd_dpm()
1518 sizeof(u8), pi->sram_end); in kv_update_uvd_dpm()
1548 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_vce_dpm() local
1554 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1555 pi->vce_boot_level = table->count - 1; in kv_update_vce_dpm()
1557 pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk); in kv_update_vce_dpm()
1560 pi->dpm_table_start + in kv_update_vce_dpm()
1562 (u8 *)&pi->vce_boot_level, in kv_update_vce_dpm()
1564 pi->sram_end); in kv_update_vce_dpm()
1568 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1571 (1 << pi->vce_boot_level)); in kv_update_vce_dpm()
1582 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_samu_dpm() local
1588 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1589 pi->samu_boot_level = table->count - 1; in kv_update_samu_dpm()
1591 pi->samu_boot_level = 0; in kv_update_samu_dpm()
1594 pi->dpm_table_start + in kv_update_samu_dpm()
1596 (u8 *)&pi->samu_boot_level, in kv_update_samu_dpm()
1598 pi->sram_end); in kv_update_samu_dpm()
1602 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1605 (1 << pi->samu_boot_level)); in kv_update_samu_dpm()
1630 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_boot_level() local
1633 if (!pi->caps_stable_p_state) { in kv_update_acp_boot_level()
1635 if (acp_boot_level != pi->acp_boot_level) { in kv_update_acp_boot_level()
1636 pi->acp_boot_level = acp_boot_level; in kv_update_acp_boot_level()
1639 (1 << pi->acp_boot_level)); in kv_update_acp_boot_level()
1646 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_dpm() local
1652 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1653 pi->acp_boot_level = table->count - 1; in kv_update_acp_dpm()
1655 pi->acp_boot_level = kv_get_acp_boot_level(adev); in kv_update_acp_dpm()
1658 pi->dpm_table_start + in kv_update_acp_dpm()
1660 (u8 *)&pi->acp_boot_level, in kv_update_acp_dpm()
1662 pi->sram_end); in kv_update_acp_dpm()
1666 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1669 (1 << pi->acp_boot_level)); in kv_update_acp_dpm()
1678 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_uvd() local
1681 pi->uvd_power_gated = gate; in kv_dpm_powergate_uvd()
1688 if (pi->caps_uvd_pg) in kv_dpm_powergate_uvd()
1692 if (pi->caps_uvd_pg) in kv_dpm_powergate_uvd()
1706 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_vce() local
1709 pi->vce_power_gated = gate; in kv_dpm_powergate_vce()
1716 if (pi->caps_vce_pg) /* power off the VCE block */ in kv_dpm_powergate_vce()
1719 if (pi->caps_vce_pg) /* power on the VCE block */ in kv_dpm_powergate_vce()
1731 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_samu() local
1733 if (pi->samu_power_gated == gate) in kv_dpm_powergate_samu()
1736 pi->samu_power_gated = gate; in kv_dpm_powergate_samu()
1740 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1743 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1751 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_acp() local
1753 if (pi->acp_power_gated == gate) in kv_dpm_powergate_acp()
1759 pi->acp_power_gated = gate; in kv_dpm_powergate_acp()
1763 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1766 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1776 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_valid_clock_range() local
1782 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1784 (i == (pi->graphics_dpm_level_count - 1))) { in kv_set_valid_clock_range()
1785 pi->lowest_valid = i; in kv_set_valid_clock_range()
1790 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1794 pi->highest_valid = i; in kv_set_valid_clock_range()
1796 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1797 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1798 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1799 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1801 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1805 &pi->sys_info.sclk_voltage_mapping_table; in kv_set_valid_clock_range()
1807 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1809 i == (int)(pi->graphics_dpm_level_count - 1)) { in kv_set_valid_clock_range()
1810 pi->lowest_valid = i; in kv_set_valid_clock_range()
1815 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1820 pi->highest_valid = i; in kv_set_valid_clock_range()
1822 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1824 table->entries[pi->highest_valid].sclk_frequency) > in kv_set_valid_clock_range()
1825 (table->entries[pi->lowest_valid].sclk_frequency - in kv_set_valid_clock_range()
1827 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1829 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1838 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_dfs_bypass_settings() local
1842 if (pi->caps_enable_dfs_bypass) { in kv_update_dfs_bypass_settings()
1844 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; in kv_update_dfs_bypass_settings()
1846 (pi->dpm_table_start + in kv_update_dfs_bypass_settings()
1848 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + in kv_update_dfs_bypass_settings()
1851 sizeof(u8), pi->sram_end); in kv_update_dfs_bypass_settings()
1860 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_nb_dpm() local
1864 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1867 pi->nb_dpm_enabled = true; in kv_enable_nb_dpm()
1870 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1873 pi->nb_dpm_enabled = false; in kv_enable_nb_dpm()
1908 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_pre_set_power_state() local
1915 &pi->requested_rps, in kv_dpm_pre_set_power_state()
1916 &pi->current_rps); in kv_dpm_pre_set_power_state()
1924 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_set_power_state() local
1925 struct amdgpu_ps *new_ps = &pi->requested_rps; in kv_dpm_set_power_state()
1926 struct amdgpu_ps *old_ps = &pi->current_rps; in kv_dpm_set_power_state()
1929 if (pi->bapm_enable) { in kv_dpm_set_power_state()
1938 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1967 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1999 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_post_set_power_state() local
2000 struct amdgpu_ps *new_ps = &pi->requested_rps; in kv_dpm_post_set_power_state()
2015 struct kv_power_info *pi = kv_get_pi(adev);
2030 kv_set_enabled_level(adev, pi->graphics_boot_level);
2038 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_max_power_limits_table() local
2040 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { in kv_construct_max_power_limits_table()
2041 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; in kv_construct_max_power_limits_table()
2043 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; in kv_construct_max_power_limits_table()
2046 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); in kv_construct_max_power_limits_table()
2049 table->mclk = pi->sys_info.nbp_memory_clock[0]; in kv_construct_max_power_limits_table()
2096 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_boot_state() local
2098 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; in kv_construct_boot_state()
2099 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; in kv_construct_boot_state()
2100 pi->boot_pl.ds_divider_index = 0; in kv_construct_boot_state()
2101 pi->boot_pl.ss_divider_index = 0; in kv_construct_boot_state()
2102 pi->boot_pl.allow_gnb_slow = 1; in kv_construct_boot_state()
2103 pi->boot_pl.force_nbp_state = 0; in kv_construct_boot_state()
2104 pi->boot_pl.display_wm = 0; in kv_construct_boot_state()
2105 pi->boot_pl.vce_wm = 0; in kv_construct_boot_state()
2151 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_sleep_divider_id_from_clock() local
2159 if (!pi->caps_sclk_ds) in kv_get_sleep_divider_id_from_clock()
2173 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_high_voltage_limit() local
2180 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
2182 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
2189 &pi->sys_info.sclk_voltage_mapping_table; in kv_get_high_voltage_limit()
2192 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
2194 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
2210 struct kv_power_info *pi = kv_get_pi(adev); in kv_apply_state_adjust_rules() local
2232 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2262 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2263 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2271 &pi->sys_info.sclk_voltage_mapping_table; in kv_apply_state_adjust_rules()
2274 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2275 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2283 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2289 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2294 pi->battery_state = true; in kv_apply_state_adjust_rules()
2296 pi->battery_state = false; in kv_apply_state_adjust_rules()
2309 if (pi->sys_info.nb_dpm_enable) { in kv_apply_state_adjust_rules()
2310 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_apply_state_adjust_rules()
2311 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2312 pi->disable_nb_ps3_in_battery; in kv_apply_state_adjust_rules()
2324 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enabled_for_throttle() local
2326 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; in kv_dpm_power_level_enabled_for_throttle()
2331 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_ds_divider() local
2335 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_ds_divider()
2338 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_ds_divider()
2339 pi->graphics_level[i].DeepSleepDivId = in kv_calculate_ds_divider()
2341 be32_to_cpu(pi->graphics_level[i].SclkFrequency), in kv_calculate_ds_divider()
2349 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_nbps_level_settings() local
2356 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_nbps_level_settings()
2360 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2361 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2362 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2363 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2366 if (!pi->sys_info.nb_dpm_enable) in kv_calculate_nbps_level_settings()
2369 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_calculate_nbps_level_settings()
2370 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2373 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_nbps_level_settings()
2374 pi->graphics_level[i].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2376 if (pi->battery_state) in kv_calculate_nbps_level_settings()
2377 pi->graphics_level[0].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2379 pi->graphics_level[1].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2380 pi->graphics_level[2].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2381 pi->graphics_level[3].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2382 pi->graphics_level[4].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2385 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2386 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2387 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2388 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2391 if (pi->sys_info.nb_dpm_enable && pi->battery_state) { in kv_calculate_nbps_level_settings()
2392 pi->graphics_level[pi->lowest_valid].UpH = 0x28; in kv_calculate_nbps_level_settings()
2393 pi->graphics_level[pi->lowest_valid].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2394 if (pi->lowest_valid != pi->highest_valid) in kv_calculate_nbps_level_settings()
2395 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2403 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dpm_settings() local
2406 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_dpm_settings()
2409 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_dpm_settings()
2410 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; in kv_calculate_dpm_settings()
2417 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_graphics_levels() local
2425 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2427 if (pi->high_voltage_t && in kv_init_graphics_levels()
2428 (pi->high_voltage_t < in kv_init_graphics_levels()
2434 &pi->sys_info.vid_mapping_table, in kv_init_graphics_levels()
2437 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2439 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2443 &pi->sys_info.sclk_voltage_mapping_table; in kv_init_graphics_levels()
2445 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2447 if (pi->high_voltage_t && in kv_init_graphics_levels()
2448 pi->high_voltage_t < in kv_init_graphics_levels()
2454 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2456 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2466 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_new_levels() local
2470 if (i >= pi->lowest_valid && i <= pi->highest_valid) in kv_enable_new_levels()
2486 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_enabled_levels() local
2489 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_set_enabled_levels()
2501 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_nbps_index_settings() local
2507 if (pi->sys_info.nb_dpm_enable) { in kv_program_nbps_index_settings()
2561 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_sys_info_table() local
2578 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); in kv_parse_sys_info_table()
2579 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); in kv_parse_sys_info_table()
2580 pi->sys_info.bootup_nb_voltage_index = in kv_parse_sys_info_table()
2583 pi->sys_info.htc_tmp_lmt = 203; in kv_parse_sys_info_table()
2585 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; in kv_parse_sys_info_table()
2587 pi->sys_info.htc_hyst_lmt = 5; in kv_parse_sys_info_table()
2589 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; in kv_parse_sys_info_table()
2590 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { in kv_parse_sys_info_table()
2595 pi->sys_info.nb_dpm_enable = true; in kv_parse_sys_info_table()
2597 pi->sys_info.nb_dpm_enable = false; in kv_parse_sys_info_table()
2600 pi->sys_info.nbp_memory_clock[i] = in kv_parse_sys_info_table()
2602 pi->sys_info.nbp_n_clock[i] = in kv_parse_sys_info_table()
2607 pi->caps_enable_dfs_bypass = true; in kv_parse_sys_info_table()
2610 &pi->sys_info.sclk_voltage_mapping_table, in kv_parse_sys_info_table()
2614 &pi->sys_info.vid_mapping_table, in kv_parse_sys_info_table()
2647 struct kv_power_info *pi = kv_get_pi(adev); in kv_patch_boot_state() local
2650 ps->levels[0] = pi->boot_pl; in kv_patch_boot_state()
2684 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_pplib_clock_info() local
2696 if (pi->caps_sclk_ds) { in kv_parse_pplib_clock_info()
2794 struct kv_power_info *pi; in kv_dpm_init() local
2797 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); in kv_dpm_init()
2798 if (pi == NULL) in kv_dpm_init()
2800 adev->pm.dpm.priv = pi; in kv_dpm_init()
2811 pi->at[i] = TRINITY_AT_DFLT; in kv_dpm_init()
2813 pi->sram_end = SMC_RAM_END; in kv_dpm_init()
2815 pi->enable_nb_dpm = true; in kv_dpm_init()
2817 pi->caps_power_containment = true; in kv_dpm_init()
2818 pi->caps_cac = true; in kv_dpm_init()
2819 pi->enable_didt = false; in kv_dpm_init()
2820 if (pi->enable_didt) { in kv_dpm_init()
2821 pi->caps_sq_ramping = true; in kv_dpm_init()
2822 pi->caps_db_ramping = true; in kv_dpm_init()
2823 pi->caps_td_ramping = true; in kv_dpm_init()
2824 pi->caps_tcp_ramping = true; in kv_dpm_init()
2828 pi->caps_sclk_ds = true; in kv_dpm_init()
2830 pi->caps_sclk_ds = false; in kv_dpm_init()
2832 pi->enable_auto_thermal_throttling = true; in kv_dpm_init()
2833 pi->disable_nb_ps3_in_battery = false; in kv_dpm_init()
2835 pi->bapm_enable = false; in kv_dpm_init()
2837 pi->bapm_enable = true; in kv_dpm_init()
2838 pi->voltage_drop_t = 0; in kv_dpm_init()
2839 pi->caps_sclk_throttle_low_notification = false; in kv_dpm_init()
2840 pi->caps_fps = false; /* true? */ in kv_dpm_init()
2841 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false; in kv_dpm_init()
2842 pi->caps_uvd_dpm = true; in kv_dpm_init()
2843 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false; in kv_dpm_init()
2844 pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false; in kv_dpm_init()
2845 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false; in kv_dpm_init()
2846 pi->caps_stable_p_state = false; in kv_dpm_init()
2859 pi->enable_dpm = true; in kv_dpm_init()
2869 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_debugfs_print_current_performance_level() local
2880 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); in kv_dpm_debugfs_print_current_performance_level()
2885 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2886 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2932 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_sclk() local
2933 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); in kv_dpm_get_sclk()
2944 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_mclk() local
2946 return pi->sys_info.bootup_uma_clk; in kv_dpm_get_mclk()
3285 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_read_sensor() local
3300 pi->graphics_level[pl_index].SclkFrequency); in kv_dpm_read_sensor()