Lines Matching refs:num_levels
1791 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1798 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1817 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1826 new_ps->levels[new_ps->num_levels -1].sclk)) in kv_set_valid_clock_range()
2255 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2261 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2273 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2284 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2649 ps->num_levels = 1; in kv_patch_boot_state()
2694 ps->num_levels = index + 1; in kv_parse_pplib_clock_info()
2903 for (i = 0; i < ps->num_levels; i++) { in kv_dpm_print_power_state()
2938 return requested_state->levels[requested_state->num_levels - 1].sclk; in kv_dpm_get_sclk()
3261 if (kv_cps->num_levels != kv_rps->num_levels) { in kv_check_state_equal()
3266 for (i = 0; i < kv_cps->num_levels; i++) { in kv_check_state_equal()