991 		pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);  in kv_populate_vce_table()
995 			(u8)kv_get_clk_bypass(adev, table->entries[i].evclk);  in kv_populate_vce_table()
998 							 table->entries[i].evclk, false, &dividers);  in kv_populate_vce_table()
1530 static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk)  in kv_get_vce_boot_level()  argument
1537 		if (table->entries[i].evclk >= evclk)  in kv_get_vce_boot_level()
1553 	if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {  in kv_update_vce_dpm()
1557 			pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk);  in kv_update_vce_dpm()
1573 	} else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) {  in kv_update_vce_dpm()
2222 		new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;  in kv_apply_state_adjust_rules()
2225 		new_rps->evclk = 0;  in kv_apply_state_adjust_rules()
2290 		new_rps->evclk || new_rps->ecclk;  in kv_apply_state_adjust_rules()
3276 	*equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));  in kv_check_state_equal()