Lines Matching refs:gmc
243 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); in gmc_v8_0_init_microcode()
246 err = amdgpu_ucode_validate(adev->gmc.fw); in gmc_v8_0_init_microcode()
251 release_firmware(adev->gmc.fw); in gmc_v8_0_init_microcode()
252 adev->gmc.fw = NULL; in gmc_v8_0_init_microcode()
281 if (!adev->gmc.fw) in gmc_v8_0_tonga_mc_load_microcode()
284 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_tonga_mc_load_microcode()
287 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_tonga_mc_load_microcode()
290 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
293 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
357 if (!adev->gmc.fw) in gmc_v8_0_polaris_mc_load_microcode()
360 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_polaris_mc_load_microcode()
363 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_polaris_mc_load_microcode()
366 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v8_0_polaris_mc_load_microcode()
369 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v8_0_polaris_mc_load_microcode()
413 amdgpu_device_vram_location(adev, &adev->gmc, base); in gmc_v8_0_vram_gtt_location()
456 adev->gmc.vram_start >> 12); in gmc_v8_0_mc_program()
458 adev->gmc.vram_end >> 12); in gmc_v8_0_mc_program()
463 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; in gmc_v8_0_mc_program()
464 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); in gmc_v8_0_mc_program()
467 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); in gmc_v8_0_mc_program()
502 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); in gmc_v8_0_mc_init()
503 if (!adev->gmc.vram_width) { in gmc_v8_0_mc_init()
545 adev->gmc.vram_width = numchan * chansize; in gmc_v8_0_mc_init()
548 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; in gmc_v8_0_mc_init()
549 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; in gmc_v8_0_mc_init()
556 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v8_0_mc_init()
557 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v8_0_mc_init()
561 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; in gmc_v8_0_mc_init()
562 adev->gmc.aper_size = adev->gmc.real_vram_size; in gmc_v8_0_mc_init()
567 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v8_0_mc_init()
568 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) in gmc_v8_0_mc_init()
569 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; in gmc_v8_0_mc_init()
579 adev->gmc.gart_size = 256ULL << 20; in gmc_v8_0_mc_init()
585 adev->gmc.gart_size = 1024ULL << 20; in gmc_v8_0_mc_init()
589 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; in gmc_v8_0_mc_init()
592 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); in gmc_v8_0_mc_init()
749 if (enable && !adev->gmc.prt_warning) { in gmc_v8_0_set_prt()
751 adev->gmc.prt_warning = true; in gmc_v8_0_set_prt()
864 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); in gmc_v8_0_gart_enable()
865 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); in gmc_v8_0_gart_enable()
920 (unsigned)(adev->gmc.gart_size >> 20), in gmc_v8_0_gart_enable()
1029 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v8_0_early_init()
1030 adev->gmc.shared_aperture_end = in gmc_v8_0_early_init()
1031 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; in gmc_v8_0_early_init()
1032 adev->gmc.private_aperture_start = in gmc_v8_0_early_init()
1033 adev->gmc.shared_aperture_end + 1; in gmc_v8_0_early_init()
1034 adev->gmc.private_aperture_end = in gmc_v8_0_early_init()
1035 adev->gmc.private_aperture_start + (4ULL << 30) - 1; in gmc_v8_0_early_init()
1047 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v8_0_late_init()
1066 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) in gmc_v8_0_get_vbios_fb_size()
1080 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; in gmc_v8_0_sw_init()
1090 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); in gmc_v8_0_sw_init()
1093 …d_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); in gmc_v8_0_sw_init()
1097 …d_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); in gmc_v8_0_sw_init()
1111 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ in gmc_v8_0_sw_init()
1143 adev->gmc.stolen_size = gmc_v8_0_get_vbios_fb_size(adev); in gmc_v8_0_sw_init()
1173 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), in gmc_v8_0_sw_init()
1175 if (!adev->gmc.vm_fault_info) in gmc_v8_0_sw_init()
1177 atomic_set(&adev->gmc.vm_fault_info_updated, 0); in gmc_v8_0_sw_init()
1188 kfree(adev->gmc.vm_fault_info); in gmc_v8_0_sw_fini()
1192 release_firmware(adev->gmc.fw); in gmc_v8_0_sw_fini()
1193 adev->gmc.fw = NULL; in gmc_v8_0_sw_fini()
1234 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); in gmc_v8_0_hw_fini()
1314 adev->gmc.srbm_soft_reset = srbm_soft_reset; in gmc_v8_0_check_soft_reset()
1317 adev->gmc.srbm_soft_reset = 0; in gmc_v8_0_check_soft_reset()
1326 if (!adev->gmc.srbm_soft_reset) in gmc_v8_0_pre_soft_reset()
1342 if (!adev->gmc.srbm_soft_reset) in gmc_v8_0_soft_reset()
1344 srbm_soft_reset = adev->gmc.srbm_soft_reset; in gmc_v8_0_soft_reset()
1372 if (!adev->gmc.srbm_soft_reset) in gmc_v8_0_post_soft_reset()
1465 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { in gmc_v8_0_process_interrupt()
1466 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; in gmc_v8_0_process_interrupt()
1482 atomic_set(&adev->gmc.vm_fault_info_updated, 1); in gmc_v8_0_process_interrupt()
1731 if (adev->gmc.gmc_funcs == NULL) in gmc_v8_0_set_gmc_funcs()
1732 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs; in gmc_v8_0_set_gmc_funcs()
1737 adev->gmc.vm_fault.num_types = 1; in gmc_v8_0_set_irq_funcs()
1738 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs; in gmc_v8_0_set_irq_funcs()