180 		WREG32(mmBIF_FB_EN, 0);  in gmc_v8_0_mc_stop()
184 		WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);  in gmc_v8_0_mc_stop()
197 	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);  in gmc_v8_0_mc_resume()
201 	WREG32(mmBIF_FB_EN, tmp);  in gmc_v8_0_mc_resume()
299 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v8_0_tonga_mc_load_microcode()
300 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);  in gmc_v8_0_tonga_mc_load_microcode()
304 			WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));  in gmc_v8_0_tonga_mc_load_microcode()
305 			WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));  in gmc_v8_0_tonga_mc_load_microcode()
309 			WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));  in gmc_v8_0_tonga_mc_load_microcode()
312 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v8_0_tonga_mc_load_microcode()
313 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);  in gmc_v8_0_tonga_mc_load_microcode()
314 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);  in gmc_v8_0_tonga_mc_load_microcode()
350 	WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);  in gmc_v8_0_polaris_mc_load_microcode()
373 	WREG32(mmMC_SEQ_MISC0, data);  in gmc_v8_0_polaris_mc_load_microcode()
377 		WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));  in gmc_v8_0_polaris_mc_load_microcode()
378 		WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));  in gmc_v8_0_polaris_mc_load_microcode()
381 	WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v8_0_polaris_mc_load_microcode()
382 	WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);  in gmc_v8_0_polaris_mc_load_microcode()
386 		WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));  in gmc_v8_0_polaris_mc_load_microcode()
389 	WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v8_0_polaris_mc_load_microcode()
390 	WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);  in gmc_v8_0_polaris_mc_load_microcode()
391 	WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);  in gmc_v8_0_polaris_mc_load_microcode()
432 		WREG32((0xb05 + j), 0x00000000);  in gmc_v8_0_mc_program()
433 		WREG32((0xb06 + j), 0x00000000);  in gmc_v8_0_mc_program()
434 		WREG32((0xb07 + j), 0x00000000);  in gmc_v8_0_mc_program()
435 		WREG32((0xb08 + j), 0x00000000);  in gmc_v8_0_mc_program()
436 		WREG32((0xb09 + j), 0x00000000);  in gmc_v8_0_mc_program()
438 	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);  in gmc_v8_0_mc_program()
447 		WREG32(mmVGA_HDP_CONTROL, tmp);  in gmc_v8_0_mc_program()
452 		WREG32(mmVGA_RENDER_CONTROL, tmp);  in gmc_v8_0_mc_program()
455 	WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,  in gmc_v8_0_mc_program()
457 	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,  in gmc_v8_0_mc_program()
459 	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,  in gmc_v8_0_mc_program()
465 		WREG32(mmMC_VM_FB_LOCATION, tmp);  in gmc_v8_0_mc_program()
467 		WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));  in gmc_v8_0_mc_program()
468 		WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));  in gmc_v8_0_mc_program()
469 		WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);  in gmc_v8_0_mc_program()
472 	WREG32(mmMC_VM_AGP_BASE, 0);  in gmc_v8_0_mc_program()
473 	WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);  in gmc_v8_0_mc_program()
474 	WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);  in gmc_v8_0_mc_program()
479 	WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);  in gmc_v8_0_mc_program()
483 	WREG32(mmHDP_MISC_CNTL, tmp);  in gmc_v8_0_mc_program()
486 	WREG32(mmHDP_HOST_PATH_CNTL, tmp);  in gmc_v8_0_mc_program()
616 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);  in gmc_v8_0_flush_gpu_tlb()
736 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_set_fault_enable_default()
769 	WREG32(mmVM_PRT_CNTL, tmp);  in gmc_v8_0_set_prt()
776 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);  in gmc_v8_0_set_prt()
777 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);  in gmc_v8_0_set_prt()
778 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);  in gmc_v8_0_set_prt()
779 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);  in gmc_v8_0_set_prt()
780 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);  in gmc_v8_0_set_prt()
781 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);  in gmc_v8_0_set_prt()
782 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);  in gmc_v8_0_set_prt()
783 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);  in gmc_v8_0_set_prt()
785 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);  in gmc_v8_0_set_prt()
786 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);  in gmc_v8_0_set_prt()
787 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);  in gmc_v8_0_set_prt()
788 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);  in gmc_v8_0_set_prt()
789 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);  in gmc_v8_0_set_prt()
790 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);  in gmc_v8_0_set_prt()
791 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);  in gmc_v8_0_set_prt()
792 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);  in gmc_v8_0_set_prt()
826 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v8_0_gart_enable()
836 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v8_0_gart_enable()
840 	WREG32(mmVM_L2_CNTL2, tmp);  in gmc_v8_0_gart_enable()
847 	WREG32(mmVM_L2_CNTL3, tmp);  in gmc_v8_0_gart_enable()
862 	WREG32(mmVM_L2_CNTL4, tmp);  in gmc_v8_0_gart_enable()
864 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);  in gmc_v8_0_gart_enable()
865 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);  in gmc_v8_0_gart_enable()
866 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);  in gmc_v8_0_gart_enable()
867 	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v8_0_gart_enable()
869 	WREG32(mmVM_CONTEXT0_CNTL2, 0);  in gmc_v8_0_gart_enable()
874 	WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v8_0_gart_enable()
876 	WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);  in gmc_v8_0_gart_enable()
877 	WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);  in gmc_v8_0_gart_enable()
878 	WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);  in gmc_v8_0_gart_enable()
885 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);  in gmc_v8_0_gart_enable()
886 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);  in gmc_v8_0_gart_enable()
889 			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,  in gmc_v8_0_gart_enable()
892 			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,  in gmc_v8_0_gart_enable()
897 	WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v8_0_gart_enable()
899 	WREG32(mmVM_CONTEXT1_CNTL2, 4);  in gmc_v8_0_gart_enable()
912 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_gart_enable()
955 	WREG32(mmVM_CONTEXT0_CNTL, 0);  in gmc_v8_0_gart_disable()
956 	WREG32(mmVM_CONTEXT1_CNTL, 0);  in gmc_v8_0_gart_disable()
962 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v8_0_gart_disable()
966 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v8_0_gart_disable()
967 	WREG32(mmVM_L2_CNTL2, 0);  in gmc_v8_0_gart_disable()
1352 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v8_0_soft_reset()
1358 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v8_0_soft_reset()
1398 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1402 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1408 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1412 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1496 		WREG32(mmMC_HUB_MISC_HUB_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1500 		WREG32(mmMC_HUB_MISC_SIP_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1504 		WREG32(mmMC_HUB_MISC_VM_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1508 		WREG32(mmMC_XPB_CLK_GAT, data);  in fiji_update_mc_medium_grain_clock_gating()
1512 		WREG32(mmATC_MISC_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1516 		WREG32(mmMC_CITF_MISC_WR_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1520 		WREG32(mmMC_CITF_MISC_RD_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1524 		WREG32(mmMC_CITF_MISC_VM_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1528 		WREG32(mmVM_L2_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1532 		WREG32(mmMC_HUB_MISC_HUB_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1536 		WREG32(mmMC_HUB_MISC_SIP_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1540 		WREG32(mmMC_HUB_MISC_VM_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1544 		WREG32(mmMC_XPB_CLK_GAT, data);  in fiji_update_mc_medium_grain_clock_gating()
1548 		WREG32(mmATC_MISC_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1552 		WREG32(mmMC_CITF_MISC_WR_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1556 		WREG32(mmMC_CITF_MISC_RD_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1560 		WREG32(mmMC_CITF_MISC_VM_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1564 		WREG32(mmVM_L2_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1576 		WREG32(mmMC_HUB_MISC_HUB_CG, data);  in fiji_update_mc_light_sleep()
1580 		WREG32(mmMC_HUB_MISC_SIP_CG, data);  in fiji_update_mc_light_sleep()
1584 		WREG32(mmMC_HUB_MISC_VM_CG, data);  in fiji_update_mc_light_sleep()
1588 		WREG32(mmMC_XPB_CLK_GAT, data);  in fiji_update_mc_light_sleep()
1592 		WREG32(mmATC_MISC_CG, data);  in fiji_update_mc_light_sleep()
1596 		WREG32(mmMC_CITF_MISC_WR_CG, data);  in fiji_update_mc_light_sleep()
1600 		WREG32(mmMC_CITF_MISC_RD_CG, data);  in fiji_update_mc_light_sleep()
1604 		WREG32(mmMC_CITF_MISC_VM_CG, data);  in fiji_update_mc_light_sleep()
1608 		WREG32(mmVM_L2_CG, data);  in fiji_update_mc_light_sleep()
1612 		WREG32(mmMC_HUB_MISC_HUB_CG, data);  in fiji_update_mc_light_sleep()
1616 		WREG32(mmMC_HUB_MISC_SIP_CG, data);  in fiji_update_mc_light_sleep()
1620 		WREG32(mmMC_HUB_MISC_VM_CG, data);  in fiji_update_mc_light_sleep()
1624 		WREG32(mmMC_XPB_CLK_GAT, data);  in fiji_update_mc_light_sleep()
1628 		WREG32(mmATC_MISC_CG, data);  in fiji_update_mc_light_sleep()
1632 		WREG32(mmMC_CITF_MISC_WR_CG, data);  in fiji_update_mc_light_sleep()
1636 		WREG32(mmMC_CITF_MISC_RD_CG, data);  in fiji_update_mc_light_sleep()
1640 		WREG32(mmMC_CITF_MISC_VM_CG, data);  in fiji_update_mc_light_sleep()
1644 		WREG32(mmVM_L2_CG, data);  in fiji_update_mc_light_sleep()