107 	u32 tmp;  in gmc_v7_0_mc_resume()  local
110 	tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);  in gmc_v7_0_mc_resume()
111 	tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);  in gmc_v7_0_mc_resume()
112 	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);  in gmc_v7_0_mc_resume()
114 	tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);  in gmc_v7_0_mc_resume()
115 	tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);  in gmc_v7_0_mc_resume()
116 	WREG32(mmBIF_FB_EN, tmp);  in gmc_v7_0_mc_resume()
258 	u32 tmp;  in gmc_v7_0_mc_program()  local
276 		tmp = RREG32(mmVGA_HDP_CONTROL);  in gmc_v7_0_mc_program()
277 		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);  in gmc_v7_0_mc_program()
278 		WREG32(mmVGA_HDP_CONTROL, tmp);  in gmc_v7_0_mc_program()
281 		tmp = RREG32(mmVGA_RENDER_CONTROL);  in gmc_v7_0_mc_program()
282 		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);  in gmc_v7_0_mc_program()
283 		WREG32(mmVGA_RENDER_CONTROL, tmp);  in gmc_v7_0_mc_program()
301 	tmp = RREG32(mmHDP_MISC_CNTL);  in gmc_v7_0_mc_program()
302 	tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);  in gmc_v7_0_mc_program()
303 	WREG32(mmHDP_MISC_CNTL, tmp);  in gmc_v7_0_mc_program()
305 	tmp = RREG32(mmHDP_HOST_PATH_CNTL);  in gmc_v7_0_mc_program()
306 	WREG32(mmHDP_HOST_PATH_CNTL, tmp);  in gmc_v7_0_mc_program()
324 		u32 tmp;  in gmc_v7_0_mc_init()  local
328 		tmp = RREG32(mmMC_ARB_RAMCFG);  in gmc_v7_0_mc_init()
329 		if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {  in gmc_v7_0_mc_init()
334 		tmp = RREG32(mmMC_SHARED_CHMAP);  in gmc_v7_0_mc_init()
335 		switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {  in gmc_v7_0_mc_init()
516 	u32 tmp;  in gmc_v7_0_set_fault_enable_default()  local
518 	tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_set_fault_enable_default()
519 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
521 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
523 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
525 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
527 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
529 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
531 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_set_fault_enable_default()
542 	uint32_t tmp;  in gmc_v7_0_set_prt()  local
549 	tmp = RREG32(mmVM_PRT_CNTL);  in gmc_v7_0_set_prt()
550 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v7_0_set_prt()
552 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v7_0_set_prt()
554 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v7_0_set_prt()
556 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v7_0_set_prt()
558 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v7_0_set_prt()
560 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v7_0_set_prt()
562 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v7_0_set_prt()
564 	WREG32(mmVM_PRT_CNTL, tmp);  in gmc_v7_0_set_prt()
605 	u32 tmp, field;  in gmc_v7_0_gart_enable()  local
615 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);  in gmc_v7_0_gart_enable()
616 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);  in gmc_v7_0_gart_enable()
617 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);  in gmc_v7_0_gart_enable()
618 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);  in gmc_v7_0_gart_enable()
619 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);  in gmc_v7_0_gart_enable()
620 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);  in gmc_v7_0_gart_enable()
621 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v7_0_gart_enable()
623 	tmp = RREG32(mmVM_L2_CNTL);  in gmc_v7_0_gart_enable()
624 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);  in gmc_v7_0_gart_enable()
625 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);  in gmc_v7_0_gart_enable()
626 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);  in gmc_v7_0_gart_enable()
627 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);  in gmc_v7_0_gart_enable()
628 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);  in gmc_v7_0_gart_enable()
629 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);  in gmc_v7_0_gart_enable()
630 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);  in gmc_v7_0_gart_enable()
631 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v7_0_gart_enable()
632 	tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);  in gmc_v7_0_gart_enable()
633 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);  in gmc_v7_0_gart_enable()
634 	WREG32(mmVM_L2_CNTL2, tmp);  in gmc_v7_0_gart_enable()
637 	tmp = RREG32(mmVM_L2_CNTL3);  in gmc_v7_0_gart_enable()
638 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);  in gmc_v7_0_gart_enable()
639 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);  in gmc_v7_0_gart_enable()
640 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);  in gmc_v7_0_gart_enable()
641 	WREG32(mmVM_L2_CNTL3, tmp);  in gmc_v7_0_gart_enable()
649 	tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_gart_enable()
650 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);  in gmc_v7_0_gart_enable()
651 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);  in gmc_v7_0_gart_enable()
652 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);  in gmc_v7_0_gart_enable()
653 	WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v7_0_gart_enable()
679 	tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_gart_enable()
680 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);  in gmc_v7_0_gart_enable()
681 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);  in gmc_v7_0_gart_enable()
682 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,  in gmc_v7_0_gart_enable()
684 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_gart_enable()
691 		tmp = RREG32(mmCHUB_CONTROL);  in gmc_v7_0_gart_enable()
692 		tmp &= ~BYPASS_VM;  in gmc_v7_0_gart_enable()
693 		WREG32(mmCHUB_CONTROL, tmp);  in gmc_v7_0_gart_enable()
730 	u32 tmp;  in gmc_v7_0_gart_disable()  local
736 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);  in gmc_v7_0_gart_disable()
737 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);  in gmc_v7_0_gart_disable()
738 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);  in gmc_v7_0_gart_disable()
739 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);  in gmc_v7_0_gart_disable()
740 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v7_0_gart_disable()
742 	tmp = RREG32(mmVM_L2_CNTL);  in gmc_v7_0_gart_disable()
743 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);  in gmc_v7_0_gart_disable()
744 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v7_0_gart_disable()
984 		u32 tmp = RREG32(mmMC_SEQ_MISC0);  in gmc_v7_0_sw_init()  local
985 		tmp &= MC_SEQ_MISC0__MT__MASK;  in gmc_v7_0_sw_init()
986 		adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);  in gmc_v7_0_sw_init()
1061 		u64 tmp = RREG32(mmMC_VM_FB_OFFSET);  in gmc_v7_0_sw_init()  local
1063 		tmp <<= 22;  in gmc_v7_0_sw_init()
1064 		adev->vm_manager.vram_base_offset = tmp;  in gmc_v7_0_sw_init()
1154 	u32 tmp = RREG32(mmSRBM_STATUS);  in gmc_v7_0_is_idle()  local
1156 	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |  in gmc_v7_0_is_idle()
1166 	u32 tmp;  in gmc_v7_0_wait_for_idle()  local
1171 		tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |  in gmc_v7_0_wait_for_idle()
1176 		if (!tmp)  in gmc_v7_0_wait_for_idle()
1188 	u32 tmp = RREG32(mmSRBM_STATUS);  in gmc_v7_0_soft_reset()  local
1190 	if (tmp & SRBM_STATUS__VMC_BUSY_MASK)  in gmc_v7_0_soft_reset()
1194 	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |  in gmc_v7_0_soft_reset()
1208 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1209 		tmp |= srbm_soft_reset;  in gmc_v7_0_soft_reset()
1210 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in gmc_v7_0_soft_reset()
1211 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v7_0_soft_reset()
1212 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1216 		tmp &= ~srbm_soft_reset;  in gmc_v7_0_soft_reset()
1217 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v7_0_soft_reset()
1218 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1235 	u32 tmp;  in gmc_v7_0_vm_fault_interrupt_state()  local
1246 		tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1247 		tmp &= ~bits;  in gmc_v7_0_vm_fault_interrupt_state()
1248 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()
1250 		tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1251 		tmp &= ~bits;  in gmc_v7_0_vm_fault_interrupt_state()
1252 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()
1256 		tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1257 		tmp |= bits;  in gmc_v7_0_vm_fault_interrupt_state()
1258 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()
1260 		tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1261 		tmp |= bits;  in gmc_v7_0_vm_fault_interrupt_state()
1262 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()