140 	err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);  in gmc_v6_0_init_microcode()
144 	err = amdgpu_ucode_validate(adev->gmc.fw);  in gmc_v6_0_init_microcode()
151 		release_firmware(adev->gmc.fw);  in gmc_v6_0_init_microcode()
152 		adev->gmc.fw = NULL;  in gmc_v6_0_init_microcode()
165 	if (!adev->gmc.fw)  in gmc_v6_0_mc_load_microcode()
168 	hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;  in gmc_v6_0_mc_load_microcode()
172 	adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);  in gmc_v6_0_mc_load_microcode()
175 		(adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));  in gmc_v6_0_mc_load_microcode()
178 		(adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));  in gmc_v6_0_mc_load_microcode()
226 	amdgpu_device_vram_location(adev, &adev->gmc, base);  in gmc_v6_0_vram_gtt_location()
263 	       adev->gmc.vram_start >> 12);  in gmc_v6_0_mc_program()
265 	       adev->gmc.vram_end >> 12);  in gmc_v6_0_mc_program()
323 	adev->gmc.vram_width = numchan * chansize;  in gmc_v6_0_mc_init()
325 	adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in gmc_v6_0_mc_init()
326 	adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in gmc_v6_0_mc_init()
333 	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);  in gmc_v6_0_mc_init()
334 	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);  in gmc_v6_0_mc_init()
335 	adev->gmc.visible_vram_size = adev->gmc.aper_size;  in gmc_v6_0_mc_init()
342 			adev->gmc.gart_size = 256ULL << 20;  in gmc_v6_0_mc_init()
348 			adev->gmc.gart_size = 1024ULL << 20;  in gmc_v6_0_mc_init()
352 		adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;  in gmc_v6_0_mc_init()
355 	gmc_v6_0_vram_gtt_location(adev, &adev->gmc);  in gmc_v6_0_mc_init()
449 	if (enable && !adev->gmc.prt_warning) {  in gmc_v6_0_set_prt()
451 		adev->gmc.prt_warning = true;  in gmc_v6_0_set_prt()
532 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);  in gmc_v6_0_gart_enable()
533 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);  in gmc_v6_0_gart_enable()
580 		 (unsigned)(adev->gmc.gart_size >> 20),  in gmc_v6_0_gart_enable()
819 		return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);  in gmc_v6_0_late_init()
838 	if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))  in gmc_v6_0_get_vbios_fb_size()
850 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;  in gmc_v6_0_sw_init()
854 		adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);  in gmc_v6_0_sw_init()
857 	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);  in gmc_v6_0_sw_init()
861 	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);  in gmc_v6_0_sw_init()
867 	adev->gmc.mc_mask = 0xffffffffffULL;  in gmc_v6_0_sw_init()
894 	adev->gmc.stolen_size = gmc_v6_0_get_vbios_fb_size(adev);  in gmc_v6_0_sw_init()
935 	release_firmware(adev->gmc.fw);  in gmc_v6_0_sw_fini()
936 	adev->gmc.fw = NULL;  in gmc_v6_0_sw_fini()
967 	amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);  in gmc_v6_0_hw_fini()
1178 	if (adev->gmc.gmc_funcs == NULL)  in gmc_v6_0_set_gmc_funcs()
1179 		adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;  in gmc_v6_0_set_gmc_funcs()
1184 	adev->gmc.vm_fault.num_types = 1;  in gmc_v6_0_set_irq_funcs()
1185 	adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs;  in gmc_v6_0_set_irq_funcs()