79 		WREG32(mmBIF_FB_EN, 0);  in gmc_v6_0_mc_stop()
83 		WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);  in gmc_v6_0_mc_stop()
97 	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);  in gmc_v6_0_mc_resume()
101 	WREG32(mmBIF_FB_EN, tmp);  in gmc_v6_0_mc_resume()
185 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v6_0_mc_load_microcode()
186 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);  in gmc_v6_0_mc_load_microcode()
190 			WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));  in gmc_v6_0_mc_load_microcode()
191 			WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));  in gmc_v6_0_mc_load_microcode()
195 			WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));  in gmc_v6_0_mc_load_microcode()
199 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v6_0_mc_load_microcode()
200 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);  in gmc_v6_0_mc_load_microcode()
201 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);  in gmc_v6_0_mc_load_microcode()
236 		WREG32((0xb05 + j), 0x00000000);  in gmc_v6_0_mc_program()
237 		WREG32((0xb06 + j), 0x00000000);  in gmc_v6_0_mc_program()
238 		WREG32((0xb07 + j), 0x00000000);  in gmc_v6_0_mc_program()
239 		WREG32((0xb08 + j), 0x00000000);  in gmc_v6_0_mc_program()
240 		WREG32((0xb09 + j), 0x00000000);  in gmc_v6_0_mc_program()
242 	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);  in gmc_v6_0_mc_program()
254 		WREG32(mmVGA_HDP_CONTROL, tmp);  in gmc_v6_0_mc_program()
259 		WREG32(mmVGA_RENDER_CONTROL, tmp);  in gmc_v6_0_mc_program()
262 	WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,  in gmc_v6_0_mc_program()
264 	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,  in gmc_v6_0_mc_program()
266 	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,  in gmc_v6_0_mc_program()
268 	WREG32(mmMC_VM_AGP_BASE, 0);  in gmc_v6_0_mc_program()
269 	WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);  in gmc_v6_0_mc_program()
270 	WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);  in gmc_v6_0_mc_program()
362 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);  in gmc_v6_0_flush_gpu_tlb()
436 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v6_0_set_fault_enable_default()
467 	WREG32(mmVM_PRT_CNTL, tmp);  in gmc_v6_0_set_prt()
474 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);  in gmc_v6_0_set_prt()
475 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);  in gmc_v6_0_set_prt()
476 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);  in gmc_v6_0_set_prt()
477 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);  in gmc_v6_0_set_prt()
478 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);  in gmc_v6_0_set_prt()
479 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);  in gmc_v6_0_set_prt()
480 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);  in gmc_v6_0_set_prt()
481 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);  in gmc_v6_0_set_prt()
483 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);  in gmc_v6_0_set_prt()
484 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);  in gmc_v6_0_set_prt()
485 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);  in gmc_v6_0_set_prt()
486 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);  in gmc_v6_0_set_prt()
487 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);  in gmc_v6_0_set_prt()
488 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);  in gmc_v6_0_set_prt()
489 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);  in gmc_v6_0_set_prt()
490 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);  in gmc_v6_0_set_prt()
507 	WREG32(mmMC_VM_MX_L1_TLB_CNTL,  in gmc_v6_0_gart_enable()
515 	WREG32(mmVM_L2_CNTL,  in gmc_v6_0_gart_enable()
522 	WREG32(mmVM_L2_CNTL2,  in gmc_v6_0_gart_enable()
527 	WREG32(mmVM_L2_CNTL3,  in gmc_v6_0_gart_enable()
532 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);  in gmc_v6_0_gart_enable()
533 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);  in gmc_v6_0_gart_enable()
534 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);  in gmc_v6_0_gart_enable()
535 	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v6_0_gart_enable()
537 	WREG32(mmVM_CONTEXT0_CNTL2, 0);  in gmc_v6_0_gart_enable()
538 	WREG32(mmVM_CONTEXT0_CNTL,  in gmc_v6_0_gart_enable()
543 	WREG32(0x575, 0);  in gmc_v6_0_gart_enable()
544 	WREG32(0x576, 0);  in gmc_v6_0_gart_enable()
545 	WREG32(0x577, 0);  in gmc_v6_0_gart_enable()
549 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);  in gmc_v6_0_gart_enable()
550 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);  in gmc_v6_0_gart_enable()
557 			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,  in gmc_v6_0_gart_enable()
560 			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,  in gmc_v6_0_gart_enable()
565 	WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v6_0_gart_enable()
567 	WREG32(mmVM_CONTEXT1_CNTL2, 4);  in gmc_v6_0_gart_enable()
568 	WREG32(mmVM_CONTEXT1_CNTL,  in gmc_v6_0_gart_enable()
616 	WREG32(mmVM_CONTEXT0_CNTL, 0);  in gmc_v6_0_gart_disable()
617 	WREG32(mmVM_CONTEXT1_CNTL, 0);  in gmc_v6_0_gart_disable()
619 	WREG32(mmMC_VM_MX_L1_TLB_CNTL,  in gmc_v6_0_gart_disable()
623 	WREG32(mmVM_L2_CNTL,  in gmc_v6_0_gart_disable()
628 	WREG32(mmVM_L2_CNTL2, 0);  in gmc_v6_0_gart_disable()
629 	WREG32(mmVM_L2_CNTL3,  in gmc_v6_0_gart_disable()
1049 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v6_0_soft_reset()
1055 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v6_0_soft_reset()
1084 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v6_0_vm_fault_interrupt_state()
1087 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v6_0_vm_fault_interrupt_state()
1092 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v6_0_vm_fault_interrupt_state()
1095 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v6_0_vm_fault_interrupt_state()