Lines Matching refs:gfx
299 adev->gfx.scratch.num_reg = 8; in gfx_v9_0_scratch_init()
300 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_scratch_init()
301 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v9_0_scratch_init()
448 release_firmware(adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
449 adev->gfx.pfp_fw = NULL; in gfx_v9_0_free_microcode()
450 release_firmware(adev->gfx.me_fw); in gfx_v9_0_free_microcode()
451 adev->gfx.me_fw = NULL; in gfx_v9_0_free_microcode()
452 release_firmware(adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
453 adev->gfx.ce_fw = NULL; in gfx_v9_0_free_microcode()
454 release_firmware(adev->gfx.rlc_fw); in gfx_v9_0_free_microcode()
455 adev->gfx.rlc_fw = NULL; in gfx_v9_0_free_microcode()
456 release_firmware(adev->gfx.mec_fw); in gfx_v9_0_free_microcode()
457 adev->gfx.mec_fw = NULL; in gfx_v9_0_free_microcode()
458 release_firmware(adev->gfx.mec2_fw); in gfx_v9_0_free_microcode()
459 adev->gfx.mec2_fw = NULL; in gfx_v9_0_free_microcode()
461 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_0_free_microcode()
468 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; in gfx_v9_0_init_rlc_ext_microcode()
469 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); in gfx_v9_0_init_rlc_ext_microcode()
470 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); in gfx_v9_0_init_rlc_ext_microcode()
471 …adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size… in gfx_v9_0_init_rlc_ext_microcode()
472 …adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl… in gfx_v9_0_init_rlc_ext_microcode()
473 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); in gfx_v9_0_init_rlc_ext_microcode()
474 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); in gfx_v9_0_init_rlc_ext_microcode()
475 …adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_b… in gfx_v9_0_init_rlc_ext_microcode()
476 …adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_o… in gfx_v9_0_init_rlc_ext_microcode()
477 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); in gfx_v9_0_init_rlc_ext_microcode()
478 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); in gfx_v9_0_init_rlc_ext_microcode()
479 …adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_b… in gfx_v9_0_init_rlc_ext_microcode()
480 …adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_o… in gfx_v9_0_init_rlc_ext_microcode()
481 adev->gfx.rlc.reg_list_format_direct_reg_list_length = in gfx_v9_0_init_rlc_ext_microcode()
519 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v9_0_init_microcode()
522 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v9_0_init_microcode()
525 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v9_0_init_microcode()
526 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v9_0_init_microcode()
527 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v9_0_init_microcode()
530 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v9_0_init_microcode()
533 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v9_0_init_microcode()
536 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v9_0_init_microcode()
537 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v9_0_init_microcode()
538 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v9_0_init_microcode()
541 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v9_0_init_microcode()
544 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v9_0_init_microcode()
547 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v9_0_init_microcode()
548 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v9_0_init_microcode()
549 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v9_0_init_microcode()
552 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); in gfx_v9_0_init_microcode()
555 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); in gfx_v9_0_init_microcode()
556 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v9_0_init_microcode()
561 adev->gfx.rlc.is_rlc_v2_1 = true; in gfx_v9_0_init_microcode()
563 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v9_0_init_microcode()
564 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v9_0_init_microcode()
565 adev->gfx.rlc.save_and_restore_offset = in gfx_v9_0_init_microcode()
567 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v9_0_init_microcode()
569 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v9_0_init_microcode()
571 adev->gfx.rlc.reg_restore_list_size = in gfx_v9_0_init_microcode()
573 adev->gfx.rlc.reg_list_format_start = in gfx_v9_0_init_microcode()
575 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v9_0_init_microcode()
577 adev->gfx.rlc.starting_offsets_start = in gfx_v9_0_init_microcode()
579 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v9_0_init_microcode()
581 adev->gfx.rlc.reg_list_size_bytes = in gfx_v9_0_init_microcode()
583 adev->gfx.rlc.register_list_format = in gfx_v9_0_init_microcode()
584 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + in gfx_v9_0_init_microcode()
585 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); in gfx_v9_0_init_microcode()
586 if (!adev->gfx.rlc.register_list_format) { in gfx_v9_0_init_microcode()
594 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); in gfx_v9_0_init_microcode()
596 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v9_0_init_microcode()
601 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); in gfx_v9_0_init_microcode()
603 if (adev->gfx.rlc.is_rlc_v2_1) in gfx_v9_0_init_microcode()
607 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v9_0_init_microcode()
610 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v9_0_init_microcode()
613 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_0_init_microcode()
614 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v9_0_init_microcode()
615 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v9_0_init_microcode()
619 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v9_0_init_microcode()
621 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v9_0_init_microcode()
625 adev->gfx.mec2_fw->data; in gfx_v9_0_init_microcode()
626 adev->gfx.mec2_fw_version = in gfx_v9_0_init_microcode()
628 adev->gfx.mec2_feature_version = in gfx_v9_0_init_microcode()
632 adev->gfx.mec2_fw = NULL; in gfx_v9_0_init_microcode()
638 info->fw = adev->gfx.pfp_fw; in gfx_v9_0_init_microcode()
645 info->fw = adev->gfx.me_fw; in gfx_v9_0_init_microcode()
652 info->fw = adev->gfx.ce_fw; in gfx_v9_0_init_microcode()
659 info->fw = adev->gfx.rlc_fw; in gfx_v9_0_init_microcode()
664 if (adev->gfx.rlc.is_rlc_v2_1 && in gfx_v9_0_init_microcode()
665 adev->gfx.rlc.save_restore_list_cntl_size_bytes && in gfx_v9_0_init_microcode()
666 adev->gfx.rlc.save_restore_list_gpm_size_bytes && in gfx_v9_0_init_microcode()
667 adev->gfx.rlc.save_restore_list_srm_size_bytes) { in gfx_v9_0_init_microcode()
670 info->fw = adev->gfx.rlc_fw; in gfx_v9_0_init_microcode()
672 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); in gfx_v9_0_init_microcode()
676 info->fw = adev->gfx.rlc_fw; in gfx_v9_0_init_microcode()
678 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); in gfx_v9_0_init_microcode()
682 info->fw = adev->gfx.rlc_fw; in gfx_v9_0_init_microcode()
684 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); in gfx_v9_0_init_microcode()
689 info->fw = adev->gfx.mec_fw; in gfx_v9_0_init_microcode()
697 info->fw = adev->gfx.mec_fw; in gfx_v9_0_init_microcode()
701 if (adev->gfx.mec2_fw) { in gfx_v9_0_init_microcode()
704 info->fw = adev->gfx.mec2_fw; in gfx_v9_0_init_microcode()
711 info->fw = adev->gfx.mec2_fw; in gfx_v9_0_init_microcode()
723 release_firmware(adev->gfx.pfp_fw); in gfx_v9_0_init_microcode()
724 adev->gfx.pfp_fw = NULL; in gfx_v9_0_init_microcode()
725 release_firmware(adev->gfx.me_fw); in gfx_v9_0_init_microcode()
726 adev->gfx.me_fw = NULL; in gfx_v9_0_init_microcode()
727 release_firmware(adev->gfx.ce_fw); in gfx_v9_0_init_microcode()
728 adev->gfx.ce_fw = NULL; in gfx_v9_0_init_microcode()
729 release_firmware(adev->gfx.rlc_fw); in gfx_v9_0_init_microcode()
730 adev->gfx.rlc_fw = NULL; in gfx_v9_0_init_microcode()
731 release_firmware(adev->gfx.mec_fw); in gfx_v9_0_init_microcode()
732 adev->gfx.mec_fw = NULL; in gfx_v9_0_init_microcode()
733 release_firmware(adev->gfx.mec2_fw); in gfx_v9_0_init_microcode()
734 adev->gfx.mec2_fw = NULL; in gfx_v9_0_init_microcode()
774 if (adev->gfx.rlc.cs_data == NULL) in gfx_v9_0_get_csb_buffer()
786 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v9_0_get_csb_buffer()
867 dst_ptr = adev->gfx.rlc.cp_table_ptr; in rv_init_cp_jump_table()
871 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in rv_init_cp_jump_table()
873 (adev->gfx.ce_fw->data + in rv_init_cp_jump_table()
879 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in rv_init_cp_jump_table()
881 (adev->gfx.pfp_fw->data + in rv_init_cp_jump_table()
887 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in rv_init_cp_jump_table()
889 (adev->gfx.me_fw->data + in rv_init_cp_jump_table()
895 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in rv_init_cp_jump_table()
897 (adev->gfx.mec_fw->data + in rv_init_cp_jump_table()
903 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; in rv_init_cp_jump_table()
905 (adev->gfx.mec2_fw->data + in rv_init_cp_jump_table()
923 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v9_0_rlc_fini()
924 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v9_0_rlc_fini()
925 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v9_0_rlc_fini()
928 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v9_0_rlc_fini()
929 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v9_0_rlc_fini()
930 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v9_0_rlc_fini()
940 adev->gfx.rlc.cs_data = gfx9_cs_data; in gfx_v9_0_rlc_init()
942 cs_data = adev->gfx.rlc.cs_data; in gfx_v9_0_rlc_init()
946 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev); in gfx_v9_0_rlc_init()
949 &adev->gfx.rlc.clear_state_obj, in gfx_v9_0_rlc_init()
950 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v9_0_rlc_init()
951 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v9_0_rlc_init()
959 dst_ptr = adev->gfx.rlc.cs_ptr; in gfx_v9_0_rlc_init()
961 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); in gfx_v9_0_rlc_init()
962 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); in gfx_v9_0_rlc_init()
963 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v9_0_rlc_init()
968 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ in gfx_v9_0_rlc_init()
969 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, in gfx_v9_0_rlc_init()
971 &adev->gfx.rlc.cp_table_obj, in gfx_v9_0_rlc_init()
972 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v9_0_rlc_init()
973 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v9_0_rlc_init()
982 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); in gfx_v9_0_rlc_init()
983 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); in gfx_v9_0_rlc_init()
995 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); in gfx_v9_0_csb_vram_pin()
999 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, in gfx_v9_0_csb_vram_pin()
1002 adev->gfx.rlc.clear_state_gpu_addr = in gfx_v9_0_csb_vram_pin()
1003 amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj); in gfx_v9_0_csb_vram_pin()
1005 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v9_0_csb_vram_pin()
1014 if (!adev->gfx.rlc.clear_state_obj) in gfx_v9_0_csb_vram_unpin()
1017 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); in gfx_v9_0_csb_vram_unpin()
1019 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); in gfx_v9_0_csb_vram_unpin()
1020 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v9_0_csb_vram_unpin()
1026 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v9_0_mec_fini()
1027 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v9_0_mec_fini()
1041 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v9_0_mec_init()
1045 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; in gfx_v9_0_mec_init()
1049 &adev->gfx.mec.hpd_eop_obj, in gfx_v9_0_mec_init()
1050 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v9_0_mec_init()
1058 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); in gfx_v9_0_mec_init()
1060 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v9_0_mec_init()
1061 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v9_0_mec_init()
1063 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_0_mec_init()
1066 (adev->gfx.mec_fw->data + in gfx_v9_0_mec_init()
1072 &adev->gfx.mec.mec_fw_obj, in gfx_v9_0_mec_init()
1073 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v9_0_mec_init()
1083 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v9_0_mec_init()
1084 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v9_0_mec_init()
1173 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; in gfx_v9_0_gpu_early_init()
1177 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1178 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1179 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1180 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
1181 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1185 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1186 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1187 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1188 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
1189 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1194 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1195 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1196 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1197 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
1198 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1208 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1209 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1210 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1211 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
1212 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1220 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v9_0_gpu_early_init()
1222 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v9_0_gpu_early_init()
1224 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1228 adev->gfx.config.max_tile_pipes = in gfx_v9_0_gpu_early_init()
1229 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v9_0_gpu_early_init()
1231 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << in gfx_v9_0_gpu_early_init()
1233 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1236 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v9_0_gpu_early_init()
1238 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1241 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v9_0_gpu_early_init()
1243 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1246 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v9_0_gpu_early_init()
1248 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1251 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v9_0_gpu_early_init()
1253 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1273 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines; in gfx_v9_0_ngg_create_buf()
1293 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo, in gfx_v9_0_ngg_fini()
1294 &adev->gfx.ngg.buf[i].gpu_addr, in gfx_v9_0_ngg_fini()
1297 memset(&adev->gfx.ngg.buf[0], 0, in gfx_v9_0_ngg_fini()
1300 adev->gfx.ngg.init = false; in gfx_v9_0_ngg_fini()
1309 if (!amdgpu_ngg || adev->gfx.ngg.init == true) in gfx_v9_0_ngg_init()
1313 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); in gfx_v9_0_ngg_init()
1314 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; in gfx_v9_0_ngg_init()
1315 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; in gfx_v9_0_ngg_init()
1316 adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); in gfx_v9_0_ngg_init()
1317 adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); in gfx_v9_0_ngg_init()
1320 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], in gfx_v9_0_ngg_init()
1329 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS], in gfx_v9_0_ngg_init()
1338 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL], in gfx_v9_0_ngg_init()
1350 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM], in gfx_v9_0_ngg_init()
1359 adev->gfx.ngg.init = true; in gfx_v9_0_ngg_init()
1368 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_ngg_en()
1377 adev->gfx.ngg.buf[NGG_PRIM].size >> 8); in gfx_v9_0_ngg_en()
1379 adev->gfx.ngg.buf[NGG_POS].size >> 8); in gfx_v9_0_ngg_en()
1383 adev->gfx.ngg.buf[NGG_CNTL].size >> 8); in gfx_v9_0_ngg_en()
1385 adev->gfx.ngg.buf[NGG_PARAM].size >> 10); in gfx_v9_0_ngg_en()
1389 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); in gfx_v9_0_ngg_en()
1393 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); in gfx_v9_0_ngg_en()
1397 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); in gfx_v9_0_ngg_en()
1401 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); in gfx_v9_0_ngg_en()
1405 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); in gfx_v9_0_ngg_en()
1409 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); in gfx_v9_0_ngg_en()
1424 adev->gfx.ngg.gds_reserve_size) >> in gfx_v9_0_ngg_en()
1433 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); in gfx_v9_0_ngg_en()
1436 adev->gfx.ngg.gds_reserve_size); in gfx_v9_0_ngg_en()
1451 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v9_0_compute_ring_init()
1453 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v9_0_compute_ring_init()
1463 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v9_0_compute_ring_init()
1468 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v9_0_compute_ring_init()
1473 &adev->gfx.eop_irq, irq_type); in gfx_v9_0_compute_ring_init()
1493 adev->gfx.mec.num_mec = 2; in gfx_v9_0_sw_init()
1496 adev->gfx.mec.num_mec = 1; in gfx_v9_0_sw_init()
1500 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v9_0_sw_init()
1501 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v9_0_sw_init()
1504 …_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_IB2_INTERRUPT_PKT, &adev->gfx.kiq.irq); in gfx_v9_0_sw_init()
1509 …_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); in gfx_v9_0_sw_init()
1515 &adev->gfx.priv_reg_irq); in gfx_v9_0_sw_init()
1521 &adev->gfx.priv_inst_irq); in gfx_v9_0_sw_init()
1525 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v9_0_sw_init()
1548 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v9_0_sw_init()
1549 ring = &adev->gfx.gfx_ring[i]; in gfx_v9_0_sw_init()
1558 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); in gfx_v9_0_sw_init()
1565 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v9_0_sw_init()
1566 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v9_0_sw_init()
1567 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v9_0_sw_init()
1588 kiq = &adev->gfx.kiq; in gfx_v9_0_sw_init()
1617 adev->gfx.ce_ram_size = 0x8000; in gfx_v9_0_sw_init()
1640 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v9_0_sw_fini()
1641 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v9_0_sw_fini()
1642 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_sw_fini()
1643 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v9_0_sw_fini()
1646 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); in gfx_v9_0_sw_fini()
1651 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v9_0_sw_fini()
1652 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v9_0_sw_fini()
1653 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v9_0_sw_fini()
1655 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v9_0_sw_fini()
1656 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v9_0_sw_fini()
1657 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v9_0_sw_fini()
1702 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v9_0_get_rb_active_bitmap()
1703 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_rb_active_bitmap()
1713 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v9_0_setup_rb()
1714 adev->gfx.config.max_sh_per_se; in gfx_v9_0_setup_rb()
1717 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_setup_rb()
1718 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_setup_rb()
1721 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v9_0_setup_rb()
1728 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v9_0_setup_rb()
1729 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v9_0_setup_rb()
1774 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); in gfx_v9_0_gpu_init()
1775 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); in gfx_v9_0_gpu_init()
1813 (adev->gfx.config.sc_prim_fifo_size_frontend << in gfx_v9_0_gpu_init()
1815 (adev->gfx.config.sc_prim_fifo_size_backend << in gfx_v9_0_gpu_init()
1817 (adev->gfx.config.sc_hiz_tile_fifo_size << in gfx_v9_0_gpu_init()
1819 (adev->gfx.config.sc_earlyz_tile_fifo_size << in gfx_v9_0_gpu_init()
1831 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_wait_for_rlc_serdes()
1832 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_wait_for_rlc_serdes()
1880 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v9_0_init_csb()
1882 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v9_0_init_csb()
1884 adev->gfx.rlc.clear_state_size); in gfx_v9_0_init_csb()
1937 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); in gfx_v9_1_init_rlc_save_restore_list()
1940 memcpy(register_list_format, adev->gfx.rlc.register_list_format, in gfx_v9_1_init_rlc_save_restore_list()
1941 adev->gfx.rlc.reg_list_format_size_bytes); in gfx_v9_1_init_rlc_save_restore_list()
1946 adev->gfx.rlc.reg_list_format_direct_reg_list_length, in gfx_v9_1_init_rlc_save_restore_list()
1947 adev->gfx.rlc.reg_list_format_size_bytes >> 2, in gfx_v9_1_init_rlc_save_restore_list()
1962 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) in gfx_v9_1_init_rlc_save_restore_list()
1964 adev->gfx.rlc.register_restore[i]); in gfx_v9_1_init_rlc_save_restore_list()
1968 adev->gfx.rlc.reg_list_format_start); in gfx_v9_1_init_rlc_save_restore_list()
1971 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) in gfx_v9_1_init_rlc_save_restore_list()
1976 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { in gfx_v9_1_init_rlc_save_restore_list()
1998 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; in gfx_v9_1_init_rlc_save_restore_list()
2001 adev->gfx.rlc.reg_restore_list_size); in gfx_v9_1_init_rlc_save_restore_list()
2006 adev->gfx.rlc.starting_offsets_start); in gfx_v9_1_init_rlc_save_restore_list()
2207 if (adev->gfx.rlc.is_rlc_v2_1) { in gfx_v9_0_init_pg()
2219 adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v9_0_init_pg()
2258 rlc_ucode_ver, adev->gfx.rlc_fw_version); in gfx_v9_0_rlc_start()
2276 if (!adev->gfx.rlc_fw) in gfx_v9_0_rlc_load_microcode()
2279 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v9_0_rlc_load_microcode()
2282 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v9_0_rlc_load_microcode()
2290 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v9_0_rlc_load_microcode()
2341 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v9_0_cp_gfx_enable()
2342 adev->gfx.gfx_ring[i].ready = false; in gfx_v9_0_cp_gfx_enable()
2356 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v9_0_cp_gfx_load_microcode()
2360 adev->gfx.pfp_fw->data; in gfx_v9_0_cp_gfx_load_microcode()
2362 adev->gfx.ce_fw->data; in gfx_v9_0_cp_gfx_load_microcode()
2364 adev->gfx.me_fw->data; in gfx_v9_0_cp_gfx_load_microcode()
2374 (adev->gfx.pfp_fw->data + in gfx_v9_0_cp_gfx_load_microcode()
2380 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
2384 (adev->gfx.ce_fw->data + in gfx_v9_0_cp_gfx_load_microcode()
2390 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
2394 (adev->gfx.me_fw->data + in gfx_v9_0_cp_gfx_load_microcode()
2400 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
2407 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_cp_gfx_start()
2413 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v9_0_cp_gfx_start()
2481 ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_cp_gfx_resume()
2546 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_cp_compute_enable()
2547 adev->gfx.compute_ring[i].ready = false; in gfx_v9_0_cp_compute_enable()
2548 adev->gfx.kiq.ring.ready = false; in gfx_v9_0_cp_compute_enable()
2560 if (!adev->gfx.mec_fw) in gfx_v9_0_cp_compute_load_microcode()
2565 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_0_cp_compute_load_microcode()
2569 (adev->gfx.mec_fw->data + in gfx_v9_0_cp_compute_load_microcode()
2577 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); in gfx_v9_0_cp_compute_load_microcode()
2579 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v9_0_cp_compute_load_microcode()
2589 adev->gfx.mec_fw_version); in gfx_v9_0_cp_compute_load_microcode()
2612 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v9_0_kiq_kcq_enable()
2618 if (!test_bit(i, adev->gfx.mec.queue_bitmap)) in gfx_v9_0_kiq_kcq_enable()
2639 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11); in gfx_v9_0_kiq_kcq_enable()
2656 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_kiq_kcq_enable()
2657 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_kiq_kcq_enable()
2993 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kiq_init_queue()
2994 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kiq_init_queue()
3016 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kiq_init_queue()
3017 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kiq_init_queue()
3027 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v9_0_kcq_init_queue()
3029 if (!adev->in_gpu_reset && !adev->gfx.in_suspend) { in gfx_v9_0_kcq_init_queue()
3039 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kcq_init_queue()
3040 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kcq_init_queue()
3043 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kcq_init_queue()
3044 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kcq_init_queue()
3063 ring = &adev->gfx.kiq.ring; in gfx_v9_0_kiq_resume()
3079 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_kiq_resume()
3080 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_kiq_resume()
3128 ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_cp_resume()
3135 ring = &adev->gfx.kiq.ring; in gfx_v9_0_cp_resume()
3141 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_cp_resume()
3142 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_cp_resume()
3248 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v9_0_hw_fini()
3249 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v9_0_hw_fini()
3252 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_hw_fini()
3253 gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]); in gfx_v9_0_hw_fini()
3269 if (!adev->in_gpu_reset && !adev->gfx.in_suspend) { in gfx_v9_0_hw_fini()
3271 soc15_grbm_select(adev, adev->gfx.kiq.ring.me, in gfx_v9_0_hw_fini()
3272 adev->gfx.kiq.ring.pipe, in gfx_v9_0_hw_fini()
3273 adev->gfx.kiq.ring.queue, 0); in gfx_v9_0_hw_fini()
3274 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring); in gfx_v9_0_hw_fini()
3291 adev->gfx.in_suspend = true; in gfx_v9_0_suspend()
3301 adev->gfx.in_suspend = false; in gfx_v9_0_resume()
3395 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v9_0_get_gpu_clock_counter()
3399 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v9_0_get_gpu_clock_counter()
3445 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; in gfx_v9_0_early_init()
3446 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; in gfx_v9_0_early_init()
3460 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v9_0_late_init()
3464 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v9_0_late_init()
3476 if (adev->gfx.rlc.in_safe_mode) in gfx_v9_0_enter_rlc_safe_mode()
3497 adev->gfx.rlc.in_safe_mode = true; in gfx_v9_0_enter_rlc_safe_mode()
3505 if (!adev->gfx.rlc.in_safe_mode) in gfx_v9_0_exit_rlc_safe_mode()
3521 adev->gfx.rlc.in_safe_mode = false; in gfx_v9_0_exit_rlc_safe_mode()
3637 adev->gfx.rlc.funcs->enter_safe_mode(adev); in gfx_v9_0_update_3d_clock_gating()
3677 adev->gfx.rlc.funcs->exit_safe_mode(adev); in gfx_v9_0_update_3d_clock_gating()
3685 adev->gfx.rlc.funcs->enter_safe_mode(adev); in gfx_v9_0_update_coarse_grain_clock_gating()
3725 adev->gfx.rlc.funcs->exit_safe_mode(adev); in gfx_v9_0_update_coarse_grain_clock_gating()
4059 pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe; in gfx_v9_0_ring_set_pipe_percent()
4079 mutex_lock(&adev->gfx.pipe_reserve_mutex); in gfx_v9_0_pipe_reserve_resources()
4082 set_bit(pipe, adev->gfx.pipe_reserve_bitmap); in gfx_v9_0_pipe_reserve_resources()
4084 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap); in gfx_v9_0_pipe_reserve_resources()
4086 if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) { in gfx_v9_0_pipe_reserve_resources()
4088 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) in gfx_v9_0_pipe_reserve_resources()
4089 gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i], in gfx_v9_0_pipe_reserve_resources()
4092 for (i = 0; i < adev->gfx.num_compute_rings; ++i) in gfx_v9_0_pipe_reserve_resources()
4093 gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i], in gfx_v9_0_pipe_reserve_resources()
4097 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) { in gfx_v9_0_pipe_reserve_resources()
4098 iring = &adev->gfx.gfx_ring[i]; in gfx_v9_0_pipe_reserve_resources()
4103 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); in gfx_v9_0_pipe_reserve_resources()
4107 for (i = 0; i < adev->gfx.num_compute_rings; ++i) { in gfx_v9_0_pipe_reserve_resources()
4108 iring = &adev->gfx.compute_ring[i]; in gfx_v9_0_pipe_reserve_resources()
4113 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); in gfx_v9_0_pipe_reserve_resources()
4118 mutex_unlock(&adev->gfx.pipe_reserve_mutex); in gfx_v9_0_pipe_reserve_resources()
4521 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v9_0_eop_irq()
4525 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_eop_irq()
4526 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_eop_irq()
4562 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); in gfx_v9_0_kiq_set_interrupt_state()
4606 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); in gfx_v9_0_kiq_irq()
4756 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; in gfx_v9_0_set_ring_funcs()
4758 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v9_0_set_ring_funcs()
4759 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; in gfx_v9_0_set_ring_funcs()
4761 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_set_ring_funcs()
4762 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; in gfx_v9_0_set_ring_funcs()
4787 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v9_0_set_irq_funcs()
4788 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; in gfx_v9_0_set_irq_funcs()
4790 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v9_0_set_irq_funcs()
4791 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; in gfx_v9_0_set_irq_funcs()
4793 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v9_0_set_irq_funcs()
4794 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; in gfx_v9_0_set_irq_funcs()
4796 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; in gfx_v9_0_set_irq_funcs()
4797 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs; in gfx_v9_0_set_irq_funcs()
4807 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; in gfx_v9_0_set_rlc_funcs()
4866 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v9_0_get_cu_active_bitmap()
4884 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_get_cu_info()
4885 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_get_cu_info()
4896 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v9_0_get_cu_info()
4898 if (counter < adev->gfx.config.max_cu_per_sh) in gfx_v9_0_get_cu_info()