Lines Matching refs:rlc
958 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
1087 adev->gfx.rlc.save_and_restore_offset = in gfx_v8_0_init_microcode()
1089 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v8_0_init_microcode()
1091 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v8_0_init_microcode()
1093 adev->gfx.rlc.reg_restore_list_size = in gfx_v8_0_init_microcode()
1095 adev->gfx.rlc.reg_list_format_start = in gfx_v8_0_init_microcode()
1097 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v8_0_init_microcode()
1099 adev->gfx.rlc.starting_offsets_start = in gfx_v8_0_init_microcode()
1101 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v8_0_init_microcode()
1103 adev->gfx.rlc.reg_list_size_bytes = in gfx_v8_0_init_microcode()
1106 adev->gfx.rlc.register_list_format = in gfx_v8_0_init_microcode()
1107 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + in gfx_v8_0_init_microcode()
1108 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); in gfx_v8_0_init_microcode()
1110 if (!adev->gfx.rlc.register_list_format) { in gfx_v8_0_init_microcode()
1118 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); in gfx_v8_0_init_microcode()
1120 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v8_0_init_microcode()
1125 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); in gfx_v8_0_init_microcode()
1264 if (adev->gfx.rlc.cs_data == NULL) in gfx_v8_0_get_csb_buffer()
1276 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v8_0_get_csb_buffer()
1316 dst_ptr = adev->gfx.rlc.cp_table_ptr; in cz_init_cp_jump_table()
1371 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL); in gfx_v8_0_rlc_fini()
1372 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL); in gfx_v8_0_rlc_fini()
1382 adev->gfx.rlc.cs_data = vi_cs_data; in gfx_v8_0_rlc_init()
1384 cs_data = adev->gfx.rlc.cs_data; in gfx_v8_0_rlc_init()
1388 adev->gfx.rlc.clear_state_size = dws = gfx_v8_0_get_csb_size(adev); in gfx_v8_0_rlc_init()
1392 &adev->gfx.rlc.clear_state_obj, in gfx_v8_0_rlc_init()
1393 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_rlc_init()
1394 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v8_0_rlc_init()
1402 dst_ptr = adev->gfx.rlc.cs_ptr; in gfx_v8_0_rlc_init()
1404 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); in gfx_v8_0_rlc_init()
1405 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v8_0_rlc_init()
1410 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ in gfx_v8_0_rlc_init()
1411 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, in gfx_v8_0_rlc_init()
1413 &adev->gfx.rlc.cp_table_obj, in gfx_v8_0_rlc_init()
1414 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v8_0_rlc_init()
1415 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v8_0_rlc_init()
1423 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); in gfx_v8_0_rlc_init()
1424 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); in gfx_v8_0_rlc_init()
2212 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v8_0_sw_fini()
2213 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_sw_fini()
2214 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v8_0_sw_fini()
2217 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v8_0_sw_fini()
2218 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v8_0_sw_fini()
2219 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v8_0_sw_fini()
3994 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v8_0_init_csb()
3996 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v8_0_init_csb()
3998 adev->gfx.rlc.clear_state_size); in gfx_v8_0_init_csb()
4061 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); in gfx_v8_0_init_save_restore_list()
4064 memcpy(register_list_format, adev->gfx.rlc.register_list_format, in gfx_v8_0_init_save_restore_list()
4065 adev->gfx.rlc.reg_list_format_size_bytes); in gfx_v8_0_init_save_restore_list()
4069 adev->gfx.rlc.reg_list_format_size_bytes >> 2, in gfx_v8_0_init_save_restore_list()
4081 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
4082 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]); in gfx_v8_0_init_save_restore_list()
4085 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start); in gfx_v8_0_init_save_restore_list()
4086 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
4089 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; in gfx_v8_0_init_save_restore_list()
4091 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size); in gfx_v8_0_init_save_restore_list()
4096 adev->gfx.rlc.starting_offsets_start); in gfx_v8_0_init_save_restore_list()
4161 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v8_0_init_pg()
5671 adev->gfx.rlc.funcs->enter_safe_mode(adev); in gfx_v8_0_set_powergating_state()
5725 adev->gfx.rlc.funcs->exit_safe_mode(adev); in gfx_v8_0_set_powergating_state()
5849 adev->gfx.rlc.in_safe_mode = true; in iceland_enter_rlc_safe_mode()
5863 if (adev->gfx.rlc.in_safe_mode) { in iceland_exit_rlc_safe_mode()
5867 adev->gfx.rlc.in_safe_mode = false; in iceland_exit_rlc_safe_mode()
5888 adev->gfx.rlc.funcs->enter_safe_mode(adev); in gfx_v8_0_update_medium_grain_clock_gating()
5984 adev->gfx.rlc.funcs->exit_safe_mode(adev); in gfx_v8_0_update_medium_grain_clock_gating()
5994 adev->gfx.rlc.funcs->enter_safe_mode(adev); in gfx_v8_0_update_coarse_grain_clock_gating()
6077 adev->gfx.rlc.funcs->exit_safe_mode(adev); in gfx_v8_0_update_coarse_grain_clock_gating()
7311 adev->gfx.rlc.funcs = &iceland_rlc_funcs; in gfx_v8_0_set_rlc_funcs()