4714 	struct vi_mqd *mqd = ring->mqd_ptr;  in gfx_v8_0_mqd_init()  local
4718 	mqd->header = 0xC0310800;  in gfx_v8_0_mqd_init()
4719 	mqd->compute_pipelinestat_enable = 0x00000001;  in gfx_v8_0_mqd_init()
4720 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;  in gfx_v8_0_mqd_init()
4721 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;  in gfx_v8_0_mqd_init()
4722 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;  in gfx_v8_0_mqd_init()
4723 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;  in gfx_v8_0_mqd_init()
4724 	mqd->compute_misc_reserved = 0x00000003;  in gfx_v8_0_mqd_init()
4725 	mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr  in gfx_v8_0_mqd_init()
4727 	mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr  in gfx_v8_0_mqd_init()
4730 	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;  in gfx_v8_0_mqd_init()
4731 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);  in gfx_v8_0_mqd_init()
4738 	mqd->cp_hqd_eop_control = tmp;  in gfx_v8_0_mqd_init()
4746 	mqd->cp_hqd_pq_doorbell_control = tmp;  in gfx_v8_0_mqd_init()
4749 	mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;  in gfx_v8_0_mqd_init()
4750 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);  in gfx_v8_0_mqd_init()
4755 	mqd->cp_mqd_control = tmp;  in gfx_v8_0_mqd_init()
4759 	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;  in gfx_v8_0_mqd_init()
4760 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);  in gfx_v8_0_mqd_init()
4775 	mqd->cp_hqd_pq_control = tmp;  in gfx_v8_0_mqd_init()
4779 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v8_0_mqd_init()
4780 	mqd->cp_hqd_pq_rptr_report_addr_hi =  in gfx_v8_0_mqd_init()
4785 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v8_0_mqd_init()
4786 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v8_0_mqd_init()
4803 	mqd->cp_hqd_pq_doorbell_control = tmp;  in gfx_v8_0_mqd_init()
4807 	mqd->cp_hqd_pq_wptr = ring->wptr;  in gfx_v8_0_mqd_init()
4808 	mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);  in gfx_v8_0_mqd_init()
4811 	mqd->cp_hqd_vmid = 0;  in gfx_v8_0_mqd_init()
4815 	mqd->cp_hqd_persistent_state = tmp;  in gfx_v8_0_mqd_init()
4821 	mqd->cp_hqd_ib_control = tmp;  in gfx_v8_0_mqd_init()
4825 	mqd->cp_hqd_iq_timer = tmp;  in gfx_v8_0_mqd_init()
4829 	mqd->cp_hqd_ctx_save_control = tmp;  in gfx_v8_0_mqd_init()
4832 	mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);  in gfx_v8_0_mqd_init()
4833 	mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);  in gfx_v8_0_mqd_init()
4834 	mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);  in gfx_v8_0_mqd_init()
4835 	mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);  in gfx_v8_0_mqd_init()
4836 	mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);  in gfx_v8_0_mqd_init()
4837 	mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);  in gfx_v8_0_mqd_init()
4838 	mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);  in gfx_v8_0_mqd_init()
4839 	mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);  in gfx_v8_0_mqd_init()
4840 	mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE);  in gfx_v8_0_mqd_init()
4841 	mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET);  in gfx_v8_0_mqd_init()
4842 	mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE);  in gfx_v8_0_mqd_init()
4843 	mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS);  in gfx_v8_0_mqd_init()
4844 	mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR);  in gfx_v8_0_mqd_init()
4845 	mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);  in gfx_v8_0_mqd_init()
4846 	mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);  in gfx_v8_0_mqd_init()
4849 	mqd->cp_hqd_active = 1;  in gfx_v8_0_mqd_init()
4855 			struct vi_mqd *mqd)  in gfx_v8_0_mqd_commit()  argument
4861 	mqd_data = &mqd->cp_mqd_base_addr_lo;  in gfx_v8_0_mqd_commit()
4876 		WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr);  in gfx_v8_0_mqd_commit()
4877 		WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr);  in gfx_v8_0_mqd_commit()
4878 		WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem);  in gfx_v8_0_mqd_commit()
4894 	struct vi_mqd *mqd = ring->mqd_ptr;  in gfx_v8_0_kiq_init_queue()  local
4902 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kiq_init_queue()
4909 		gfx_v8_0_mqd_commit(adev, mqd);  in gfx_v8_0_kiq_init_queue()
4913 		memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kiq_init_queue()
4914 		((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;  in gfx_v8_0_kiq_init_queue()
4915 		((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;  in gfx_v8_0_kiq_init_queue()
4919 		gfx_v8_0_mqd_commit(adev, mqd);  in gfx_v8_0_kiq_init_queue()
4924 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kiq_init_queue()
4933 	struct vi_mqd *mqd = ring->mqd_ptr;  in gfx_v8_0_kcq_init_queue()  local
4937 		memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kcq_init_queue()
4938 		((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;  in gfx_v8_0_kcq_init_queue()
4939 		((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;  in gfx_v8_0_kcq_init_queue()
4947 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kcq_init_queue()
4951 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kcq_init_queue()