Lines Matching refs:gfx
828 adev->gfx.scratch.num_reg = 8; in gfx_v8_0_scratch_init()
829 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v8_0_scratch_init()
830 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v8_0_scratch_init()
943 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
944 adev->gfx.pfp_fw = NULL; in gfx_v8_0_free_microcode()
945 release_firmware(adev->gfx.me_fw); in gfx_v8_0_free_microcode()
946 adev->gfx.me_fw = NULL; in gfx_v8_0_free_microcode()
947 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
948 adev->gfx.ce_fw = NULL; in gfx_v8_0_free_microcode()
949 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
950 adev->gfx.rlc_fw = NULL; in gfx_v8_0_free_microcode()
951 release_firmware(adev->gfx.mec_fw); in gfx_v8_0_free_microcode()
952 adev->gfx.mec_fw = NULL; in gfx_v8_0_free_microcode()
955 release_firmware(adev->gfx.mec2_fw); in gfx_v8_0_free_microcode()
956 adev->gfx.mec2_fw = NULL; in gfx_v8_0_free_microcode()
958 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
1008 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1011 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1015 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1019 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v8_0_init_microcode()
1022 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v8_0_init_microcode()
1023 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1024 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1028 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1031 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1035 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1039 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v8_0_init_microcode()
1042 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v8_0_init_microcode()
1043 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1045 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1049 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1052 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1056 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1060 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v8_0_init_microcode()
1063 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v8_0_init_microcode()
1064 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1065 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1071 if (adev->gfx.ce_feature_version >= 46 && in gfx_v8_0_init_microcode()
1072 adev->gfx.pfp_feature_version >= 46) { in gfx_v8_0_init_microcode()
1079 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1082 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); in gfx_v8_0_init_microcode()
1083 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v8_0_init_microcode()
1084 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1085 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1087 adev->gfx.rlc.save_and_restore_offset = in gfx_v8_0_init_microcode()
1089 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v8_0_init_microcode()
1091 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v8_0_init_microcode()
1093 adev->gfx.rlc.reg_restore_list_size = in gfx_v8_0_init_microcode()
1095 adev->gfx.rlc.reg_list_format_start = in gfx_v8_0_init_microcode()
1097 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v8_0_init_microcode()
1099 adev->gfx.rlc.starting_offsets_start = in gfx_v8_0_init_microcode()
1101 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v8_0_init_microcode()
1103 adev->gfx.rlc.reg_list_size_bytes = in gfx_v8_0_init_microcode()
1106 adev->gfx.rlc.register_list_format = in gfx_v8_0_init_microcode()
1107 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + in gfx_v8_0_init_microcode()
1108 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); in gfx_v8_0_init_microcode()
1110 if (!adev->gfx.rlc.register_list_format) { in gfx_v8_0_init_microcode()
1118 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); in gfx_v8_0_init_microcode()
1120 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v8_0_init_microcode()
1125 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); in gfx_v8_0_init_microcode()
1129 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1132 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1136 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1140 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v8_0_init_microcode()
1143 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v8_0_init_microcode()
1144 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1145 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1151 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1154 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1158 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1161 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v8_0_init_microcode()
1165 adev->gfx.mec2_fw->data; in gfx_v8_0_init_microcode()
1166 adev->gfx.mec2_fw_version = in gfx_v8_0_init_microcode()
1168 adev->gfx.mec2_feature_version = in gfx_v8_0_init_microcode()
1172 adev->gfx.mec2_fw = NULL; in gfx_v8_0_init_microcode()
1179 info->fw = adev->gfx.pfp_fw; in gfx_v8_0_init_microcode()
1186 info->fw = adev->gfx.me_fw; in gfx_v8_0_init_microcode()
1193 info->fw = adev->gfx.ce_fw; in gfx_v8_0_init_microcode()
1200 info->fw = adev->gfx.rlc_fw; in gfx_v8_0_init_microcode()
1207 info->fw = adev->gfx.mec_fw; in gfx_v8_0_init_microcode()
1213 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v8_0_init_microcode()
1220 info->fw = adev->gfx.mec_fw; in gfx_v8_0_init_microcode()
1225 if (adev->gfx.mec2_fw) { in gfx_v8_0_init_microcode()
1228 info->fw = adev->gfx.mec2_fw; in gfx_v8_0_init_microcode()
1241 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_init_microcode()
1242 adev->gfx.pfp_fw = NULL; in gfx_v8_0_init_microcode()
1243 release_firmware(adev->gfx.me_fw); in gfx_v8_0_init_microcode()
1244 adev->gfx.me_fw = NULL; in gfx_v8_0_init_microcode()
1245 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_init_microcode()
1246 adev->gfx.ce_fw = NULL; in gfx_v8_0_init_microcode()
1247 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_init_microcode()
1248 adev->gfx.rlc_fw = NULL; in gfx_v8_0_init_microcode()
1249 release_firmware(adev->gfx.mec_fw); in gfx_v8_0_init_microcode()
1250 adev->gfx.mec_fw = NULL; in gfx_v8_0_init_microcode()
1251 release_firmware(adev->gfx.mec2_fw); in gfx_v8_0_init_microcode()
1252 adev->gfx.mec2_fw = NULL; in gfx_v8_0_init_microcode()
1264 if (adev->gfx.rlc.cs_data == NULL) in gfx_v8_0_get_csb_buffer()
1276 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v8_0_get_csb_buffer()
1294 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); in gfx_v8_0_get_csb_buffer()
1295 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v8_0_get_csb_buffer()
1316 dst_ptr = adev->gfx.rlc.cp_table_ptr; in cz_init_cp_jump_table()
1320 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in cz_init_cp_jump_table()
1322 (adev->gfx.ce_fw->data + in cz_init_cp_jump_table()
1328 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in cz_init_cp_jump_table()
1330 (adev->gfx.pfp_fw->data + in cz_init_cp_jump_table()
1336 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in cz_init_cp_jump_table()
1338 (adev->gfx.me_fw->data + in cz_init_cp_jump_table()
1344 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in cz_init_cp_jump_table()
1346 (adev->gfx.mec_fw->data + in cz_init_cp_jump_table()
1352 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; in cz_init_cp_jump_table()
1354 (adev->gfx.mec2_fw->data + in cz_init_cp_jump_table()
1371 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL); in gfx_v8_0_rlc_fini()
1372 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL); in gfx_v8_0_rlc_fini()
1382 adev->gfx.rlc.cs_data = vi_cs_data; in gfx_v8_0_rlc_init()
1384 cs_data = adev->gfx.rlc.cs_data; in gfx_v8_0_rlc_init()
1388 adev->gfx.rlc.clear_state_size = dws = gfx_v8_0_get_csb_size(adev); in gfx_v8_0_rlc_init()
1392 &adev->gfx.rlc.clear_state_obj, in gfx_v8_0_rlc_init()
1393 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_rlc_init()
1394 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v8_0_rlc_init()
1402 dst_ptr = adev->gfx.rlc.cs_ptr; in gfx_v8_0_rlc_init()
1404 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); in gfx_v8_0_rlc_init()
1405 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v8_0_rlc_init()
1410 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ in gfx_v8_0_rlc_init()
1411 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, in gfx_v8_0_rlc_init()
1413 &adev->gfx.rlc.cp_table_obj, in gfx_v8_0_rlc_init()
1414 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v8_0_rlc_init()
1415 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v8_0_rlc_init()
1423 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); in gfx_v8_0_rlc_init()
1424 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); in gfx_v8_0_rlc_init()
1432 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v8_0_mec_fini()
1441 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v8_0_mec_init()
1446 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE; in gfx_v8_0_mec_init()
1450 &adev->gfx.mec.hpd_eop_obj, in gfx_v8_0_mec_init()
1451 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v8_0_mec_init()
1460 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_init()
1461 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_init()
1622 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; in gfx_v8_0_do_edc_gpr_workarounds()
1793 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1794 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1795 adev->gfx.config.max_cu_per_sh = 6; in gfx_v8_0_gpu_early_init()
1796 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1797 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1798 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1799 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1800 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1801 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1803 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1804 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1805 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1806 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1810 adev->gfx.config.max_shader_engines = 4; in gfx_v8_0_gpu_early_init()
1811 adev->gfx.config.max_tile_pipes = 16; in gfx_v8_0_gpu_early_init()
1812 adev->gfx.config.max_cu_per_sh = 16; in gfx_v8_0_gpu_early_init()
1813 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1814 adev->gfx.config.max_backends_per_se = 4; in gfx_v8_0_gpu_early_init()
1815 adev->gfx.config.max_texture_channel_caches = 16; in gfx_v8_0_gpu_early_init()
1816 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1817 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1818 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1820 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1821 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1822 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1823 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1831 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1832 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1833 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1835 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1836 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1837 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1838 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1846 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1847 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1848 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1850 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1851 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1852 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1853 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1857 adev->gfx.config.max_shader_engines = 4; in gfx_v8_0_gpu_early_init()
1858 adev->gfx.config.max_tile_pipes = 8; in gfx_v8_0_gpu_early_init()
1859 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()
1860 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1861 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1862 adev->gfx.config.max_texture_channel_caches = 8; in gfx_v8_0_gpu_early_init()
1863 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1864 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1865 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1867 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1868 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1869 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1870 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1874 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1875 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1876 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1877 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1878 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()
1879 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1880 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1881 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1882 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1884 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1885 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1886 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1887 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1891 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1892 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1893 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1894 adev->gfx.config.max_backends_per_se = 1; in gfx_v8_0_gpu_early_init()
1895 adev->gfx.config.max_cu_per_sh = 3; in gfx_v8_0_gpu_early_init()
1896 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1897 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1898 adev->gfx.config.max_gs_threads = 16; in gfx_v8_0_gpu_early_init()
1899 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1901 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1902 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1903 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1904 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1908 adev->gfx.config.max_shader_engines = 2; in gfx_v8_0_gpu_early_init()
1909 adev->gfx.config.max_tile_pipes = 4; in gfx_v8_0_gpu_early_init()
1910 adev->gfx.config.max_cu_per_sh = 2; in gfx_v8_0_gpu_early_init()
1911 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1912 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1913 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v8_0_gpu_early_init()
1914 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1915 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1916 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1918 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1919 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1920 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1921 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1927 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v8_0_gpu_early_init()
1928 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; in gfx_v8_0_gpu_early_init()
1930 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v8_0_gpu_early_init()
1931 adev->gfx.config.mem_max_burst_length_bytes = 256; in gfx_v8_0_gpu_early_init()
1955 adev->gfx.config.mem_row_size_in_kb = 2; in gfx_v8_0_gpu_early_init()
1957 adev->gfx.config.mem_row_size_in_kb = 1; in gfx_v8_0_gpu_early_init()
1960 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in gfx_v8_0_gpu_early_init()
1961 if (adev->gfx.config.mem_row_size_in_kb > 4) in gfx_v8_0_gpu_early_init()
1962 adev->gfx.config.mem_row_size_in_kb = 4; in gfx_v8_0_gpu_early_init()
1965 adev->gfx.config.shader_engine_tile_size = 32; in gfx_v8_0_gpu_early_init()
1966 adev->gfx.config.num_gpus = 1; in gfx_v8_0_gpu_early_init()
1967 adev->gfx.config.multi_gpu_tile_size = 64; in gfx_v8_0_gpu_early_init()
1970 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v8_0_gpu_early_init()
1982 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v8_0_gpu_early_init()
1992 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v8_0_compute_ring_init()
1994 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v8_0_compute_ring_init()
2004 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v8_0_compute_ring_init()
2009 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v8_0_compute_ring_init()
2014 &adev->gfx.eop_irq, irq_type); in gfx_v8_0_compute_ring_init()
2039 adev->gfx.mec.num_mec = 2; in gfx_v8_0_sw_init()
2044 adev->gfx.mec.num_mec = 1; in gfx_v8_0_sw_init()
2048 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v8_0_sw_init()
2049 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v8_0_sw_init()
2052 …r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_INT_IB2, &adev->gfx.… in gfx_v8_0_sw_init()
2057 …rq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq); in gfx_v8_0_sw_init()
2063 &adev->gfx.priv_reg_irq); in gfx_v8_0_sw_init()
2069 &adev->gfx.priv_inst_irq); in gfx_v8_0_sw_init()
2075 &adev->gfx.cp_ecc_error_irq); in gfx_v8_0_sw_init()
2081 &adev->gfx.sq_irq); in gfx_v8_0_sw_init()
2087 INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func); in gfx_v8_0_sw_init()
2089 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v8_0_sw_init()
2112 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v8_0_sw_init()
2113 ring = &adev->gfx.gfx_ring[i]; in gfx_v8_0_sw_init()
2122 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, in gfx_v8_0_sw_init()
2131 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v8_0_sw_init()
2132 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v8_0_sw_init()
2133 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v8_0_sw_init()
2154 kiq = &adev->gfx.kiq; in gfx_v8_0_sw_init()
2183 adev->gfx.ce_ram_size = 0x8000; in gfx_v8_0_sw_init()
2201 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_sw_fini()
2202 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v8_0_sw_fini()
2203 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_sw_fini()
2204 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v8_0_sw_fini()
2207 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); in gfx_v8_0_sw_fini()
2212 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v8_0_sw_fini()
2213 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_sw_fini()
2214 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v8_0_sw_fini()
2217 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v8_0_sw_fini()
2218 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v8_0_sw_fini()
2219 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v8_0_sw_fini()
2229 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v8_0_tiling_mode_table_init()
2230 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in gfx_v8_0_tiling_mode_table_init()
2233 modearray = adev->gfx.config.tile_mode_array; in gfx_v8_0_tiling_mode_table_init()
2234 mod2array = adev->gfx.config.macrotile_mode_array; in gfx_v8_0_tiling_mode_table_init()
3586 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v8_0_get_rb_active_bitmap()
3587 adev->gfx.config.max_sh_per_se); in gfx_v8_0_get_rb_active_bitmap()
3638 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v8_0_write_harvested_raster_configs()
3639 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v8_0_write_harvested_raster_configs()
3748 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v8_0_setup_rb()
3749 adev->gfx.config.max_sh_per_se; in gfx_v8_0_setup_rb()
3753 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_setup_rb()
3754 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3757 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v8_0_setup_rb()
3763 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v8_0_setup_rb()
3764 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v8_0_setup_rb()
3766 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v8_0_setup_rb()
3767 adev->gfx.config.max_shader_engines, 16); in gfx_v8_0_setup_rb()
3771 if (!adev->gfx.config.backend_enable_mask || in gfx_v8_0_setup_rb()
3772 adev->gfx.config.num_rbs >= num_rb_pipes) { in gfx_v8_0_setup_rb()
3777 adev->gfx.config.backend_enable_mask, in gfx_v8_0_setup_rb()
3782 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_setup_rb()
3783 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3785 adev->gfx.config.rb_config[i][j].rb_backend_disable = in gfx_v8_0_setup_rb()
3787 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = in gfx_v8_0_setup_rb()
3789 adev->gfx.config.rb_config[i][j].raster_config = in gfx_v8_0_setup_rb()
3791 adev->gfx.config.rb_config[i][j].raster_config_1 = in gfx_v8_0_setup_rb()
3848 adev->gfx.config.double_offchip_lds_buf = 1; in gfx_v8_0_config_init()
3852 adev->gfx.config.double_offchip_lds_buf = 0; in gfx_v8_0_config_init()
3863 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_gpu_init()
3864 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_gpu_init()
3865 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); in gfx_v8_0_gpu_init()
3919 (adev->gfx.config.sc_prim_fifo_size_frontend << in gfx_v8_0_gpu_init()
3921 (adev->gfx.config.sc_prim_fifo_size_backend << in gfx_v8_0_gpu_init()
3923 (adev->gfx.config.sc_hiz_tile_fifo_size << in gfx_v8_0_gpu_init()
3925 (adev->gfx.config.sc_earlyz_tile_fifo_size << in gfx_v8_0_gpu_init()
3945 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_wait_for_rlc_serdes()
3946 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_wait_for_rlc_serdes()
3994 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v8_0_init_csb()
3996 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v8_0_init_csb()
3998 adev->gfx.rlc.clear_state_size); in gfx_v8_0_init_csb()
4061 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); in gfx_v8_0_init_save_restore_list()
4064 memcpy(register_list_format, adev->gfx.rlc.register_list_format, in gfx_v8_0_init_save_restore_list()
4065 adev->gfx.rlc.reg_list_format_size_bytes); in gfx_v8_0_init_save_restore_list()
4069 adev->gfx.rlc.reg_list_format_size_bytes >> 2, in gfx_v8_0_init_save_restore_list()
4081 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
4082 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]); in gfx_v8_0_init_save_restore_list()
4085 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start); in gfx_v8_0_init_save_restore_list()
4086 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
4089 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; in gfx_v8_0_init_save_restore_list()
4091 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size); in gfx_v8_0_init_save_restore_list()
4096 adev->gfx.rlc.starting_offsets_start); in gfx_v8_0_init_save_restore_list()
4161 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v8_0_init_pg()
4163 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); in gfx_v8_0_init_pg()
4209 if (!adev->gfx.rlc_fw) in gfx_v8_0_rlc_load_microcode()
4212 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v8_0_rlc_load_microcode()
4215 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v8_0_rlc_load_microcode()
4222 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v8_0_rlc_load_microcode()
4280 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_cp_gfx_enable()
4281 adev->gfx.gfx_ring[i].ready = false; in gfx_v8_0_cp_gfx_enable()
4295 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v8_0_cp_gfx_load_microcode()
4299 adev->gfx.pfp_fw->data; in gfx_v8_0_cp_gfx_load_microcode()
4301 adev->gfx.ce_fw->data; in gfx_v8_0_cp_gfx_load_microcode()
4303 adev->gfx.me_fw->data; in gfx_v8_0_cp_gfx_load_microcode()
4313 (adev->gfx.pfp_fw->data + in gfx_v8_0_cp_gfx_load_microcode()
4319 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v8_0_cp_gfx_load_microcode()
4323 (adev->gfx.ce_fw->data + in gfx_v8_0_cp_gfx_load_microcode()
4329 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v8_0_cp_gfx_load_microcode()
4333 (adev->gfx.me_fw->data + in gfx_v8_0_cp_gfx_load_microcode()
4339 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v8_0_cp_gfx_load_microcode()
4375 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_start()
4381 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v8_0_cp_gfx_start()
4417 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); in gfx_v8_0_cp_gfx_start()
4418 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v8_0_cp_gfx_start()
4485 ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_resume()
4536 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_cp_compute_enable()
4537 adev->gfx.compute_ring[i].ready = false; in gfx_v8_0_cp_compute_enable()
4538 adev->gfx.kiq.ring.ready = false; in gfx_v8_0_cp_compute_enable()
4549 if (!adev->gfx.mec_fw) in gfx_v8_0_cp_compute_load_microcode()
4554 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v8_0_cp_compute_load_microcode()
4558 (adev->gfx.mec_fw->data + in gfx_v8_0_cp_compute_load_microcode()
4566 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v8_0_cp_compute_load_microcode()
4569 if (adev->gfx.mec2_fw) { in gfx_v8_0_cp_compute_load_microcode()
4572 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; in gfx_v8_0_cp_compute_load_microcode()
4576 (adev->gfx.mec2_fw->data + in gfx_v8_0_cp_compute_load_microcode()
4583 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version); in gfx_v8_0_cp_compute_load_microcode()
4606 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v8_0_kiq_kcq_enable()
4612 if (!test_bit(i, adev->gfx.mec.queue_bitmap)) in gfx_v8_0_kiq_kcq_enable()
4633 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 11); in gfx_v8_0_kiq_kcq_enable()
4648 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kiq_kcq_enable()
4649 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kiq_kcq_enable()
4901 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kiq_init_queue()
4902 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kiq_init_queue()
4923 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kiq_init_queue()
4924 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kiq_init_queue()
4934 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v8_0_kcq_init_queue()
4936 if (!adev->in_gpu_reset && !adev->gfx.in_suspend) { in gfx_v8_0_kcq_init_queue()
4946 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kcq_init_queue()
4947 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kcq_init_queue()
4950 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kcq_init_queue()
4951 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kcq_init_queue()
4978 ring = &adev->gfx.kiq.ring; in gfx_v8_0_kiq_resume()
4994 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kiq_resume()
4995 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kiq_resume()
5018 ring = &adev->gfx.kiq.ring; in gfx_v8_0_kiq_resume()
5027 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kiq_resume()
5028 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kiq_resume()
5149 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v8_0_hw_fini()
5150 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v8_0_hw_fini()
5152 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v8_0_hw_fini()
5154 amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0); in gfx_v8_0_hw_fini()
5157 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_hw_fini()
5158 gfx_v8_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]); in gfx_v8_0_hw_fini()
5177 adev->gfx.in_suspend = true; in gfx_v8_0_suspend()
5187 adev->gfx.in_suspend = false; in gfx_v8_0_resume()
5267 adev->gfx.grbm_soft_reset = grbm_soft_reset; in gfx_v8_0_check_soft_reset()
5268 adev->gfx.srbm_soft_reset = srbm_soft_reset; in gfx_v8_0_check_soft_reset()
5271 adev->gfx.grbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
5272 adev->gfx.srbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
5282 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_pre_soft_reset()
5283 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_pre_soft_reset()
5286 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_pre_soft_reset()
5287 srbm_soft_reset = adev->gfx.srbm_soft_reset; in gfx_v8_0_pre_soft_reset()
5303 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_pre_soft_reset()
5304 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_pre_soft_reset()
5325 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_soft_reset()
5326 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_soft_reset()
5329 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_soft_reset()
5330 srbm_soft_reset = adev->gfx.srbm_soft_reset; in gfx_v8_0_soft_reset()
5386 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_post_soft_reset()
5387 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_post_soft_reset()
5390 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_post_soft_reset()
5391 srbm_soft_reset = adev->gfx.srbm_soft_reset; in gfx_v8_0_post_soft_reset()
5403 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_post_soft_reset()
5404 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_post_soft_reset()
5431 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v8_0_get_gpu_clock_counter()
5435 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v8_0_get_gpu_clock_counter()
5558 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; in gfx_v8_0_early_init()
5559 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; in gfx_v8_0_early_init()
5560 adev->gfx.funcs = &gfx_v8_0_gfx_funcs; in gfx_v8_0_early_init()
5574 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v8_0_late_init()
5578 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v8_0_late_init()
5587 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v8_0_late_init()
5593 r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0); in gfx_v8_0_late_init()
5671 adev->gfx.rlc.funcs->enter_safe_mode(adev); in gfx_v8_0_set_powergating_state()
5725 adev->gfx.rlc.funcs->exit_safe_mode(adev); in gfx_v8_0_set_powergating_state()
5849 adev->gfx.rlc.in_safe_mode = true; in iceland_enter_rlc_safe_mode()
5863 if (adev->gfx.rlc.in_safe_mode) { in iceland_exit_rlc_safe_mode()
5867 adev->gfx.rlc.in_safe_mode = false; in iceland_exit_rlc_safe_mode()
5888 adev->gfx.rlc.funcs->enter_safe_mode(adev); in gfx_v8_0_update_medium_grain_clock_gating()
5984 adev->gfx.rlc.funcs->exit_safe_mode(adev); in gfx_v8_0_update_medium_grain_clock_gating()
5994 adev->gfx.rlc.funcs->enter_safe_mode(adev); in gfx_v8_0_update_coarse_grain_clock_gating()
6077 adev->gfx.rlc.funcs->exit_safe_mode(adev); in gfx_v8_0_update_coarse_grain_clock_gating()
6487 pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe; in gfx_v8_0_ring_set_pipe_percent()
6507 mutex_lock(&adev->gfx.pipe_reserve_mutex); in gfx_v8_0_pipe_reserve_resources()
6510 set_bit(pipe, adev->gfx.pipe_reserve_bitmap); in gfx_v8_0_pipe_reserve_resources()
6512 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap); in gfx_v8_0_pipe_reserve_resources()
6514 if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) { in gfx_v8_0_pipe_reserve_resources()
6516 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) in gfx_v8_0_pipe_reserve_resources()
6517 gfx_v8_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i], in gfx_v8_0_pipe_reserve_resources()
6520 for (i = 0; i < adev->gfx.num_compute_rings; ++i) in gfx_v8_0_pipe_reserve_resources()
6521 gfx_v8_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i], in gfx_v8_0_pipe_reserve_resources()
6525 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) { in gfx_v8_0_pipe_reserve_resources()
6526 iring = &adev->gfx.gfx_ring[i]; in gfx_v8_0_pipe_reserve_resources()
6531 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); in gfx_v8_0_pipe_reserve_resources()
6535 for (i = 0; i < adev->gfx.num_compute_rings; ++i) { in gfx_v8_0_pipe_reserve_resources()
6536 iring = &adev->gfx.compute_ring[i]; in gfx_v8_0_pipe_reserve_resources()
6541 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); in gfx_v8_0_pipe_reserve_resources()
6546 mutex_unlock(&adev->gfx.pipe_reserve_mutex); in gfx_v8_0_pipe_reserve_resources()
6935 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v8_0_eop_irq()
6939 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_eop_irq()
6940 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_eop_irq()
7051 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.sq_work.work); in gfx_v8_0_sq_irq_work_func()
7068 if (work_pending(&adev->gfx.sq_work.work)) { in gfx_v8_0_sq_irq()
7071 adev->gfx.sq_work.ih_data = ih_data; in gfx_v8_0_sq_irq()
7072 schedule_work(&adev->gfx.sq_work.work); in gfx_v8_0_sq_irq()
7083 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); in gfx_v8_0_kiq_set_interrupt_state()
7112 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); in gfx_v8_0_kiq_irq()
7249 adev->gfx.kiq.ring.funcs = &gfx_v8_0_ring_funcs_kiq; in gfx_v8_0_set_ring_funcs()
7251 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_set_ring_funcs()
7252 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx; in gfx_v8_0_set_ring_funcs()
7254 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_set_ring_funcs()
7255 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute; in gfx_v8_0_set_ring_funcs()
7290 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v8_0_set_irq_funcs()
7291 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; in gfx_v8_0_set_irq_funcs()
7293 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7294 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; in gfx_v8_0_set_irq_funcs()
7296 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7297 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs; in gfx_v8_0_set_irq_funcs()
7299 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; in gfx_v8_0_set_irq_funcs()
7300 adev->gfx.kiq.irq.funcs = &gfx_v8_0_kiq_irq_funcs; in gfx_v8_0_set_irq_funcs()
7302 adev->gfx.cp_ecc_error_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7303 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs; in gfx_v8_0_set_irq_funcs()
7305 adev->gfx.sq_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7306 adev->gfx.sq_irq.funcs = &gfx_v8_0_sq_irq_funcs; in gfx_v8_0_set_irq_funcs()
7311 adev->gfx.rlc.funcs = &iceland_rlc_funcs; in gfx_v8_0_set_rlc_funcs()
7363 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v8_0_get_cu_active_bitmap()
7372 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v8_0_get_cu_info()
7381 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v8_0_get_cu_info()
7386 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_get_cu_info()
7387 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_get_cu_info()
7398 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v8_0_get_cu_info()