2765 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);  in gfx_v7_0_mec_fini()
2774 	bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);  in gfx_v7_0_mec_init()
2780 	mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec  in gfx_v7_0_mec_init()
2785 				      &adev->gfx.mec.hpd_eop_obj,  in gfx_v7_0_mec_init()
2786 				      &adev->gfx.mec.hpd_eop_gpu_addr,  in gfx_v7_0_mec_init()
2797 	amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);  in gfx_v7_0_mec_init()
2798 	amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);  in gfx_v7_0_mec_init()
2843 				       int mec, int pipe)  in gfx_v7_0_compute_pipe_init()  argument
2847 	size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe)  in gfx_v7_0_compute_pipe_init()
2851 	eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset;  in gfx_v7_0_compute_pipe_init()
2853 	cik_srbm_select(adev, mec + 1, pipe, 0, 0);  in gfx_v7_0_compute_pipe_init()
3092 	for (i = 0; i < adev->gfx.mec.num_mec; i++)  in gfx_v7_0_cp_compute_resume()
3093 		for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++)  in gfx_v7_0_cp_compute_resume()
4464 					int mec, int pipe, int queue)  in gfx_v7_0_compute_ring_init()  argument
4471 	ring->me = mec + 1;  in gfx_v7_0_compute_ring_init()
4481 		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)  in gfx_v7_0_compute_ring_init()
4502 		adev->gfx.mec.num_mec = 2;  in gfx_v7_0_sw_init()
4509 		adev->gfx.mec.num_mec = 1;  in gfx_v7_0_sw_init()
4512 	adev->gfx.mec.num_pipe_per_mec = 4;  in gfx_v7_0_sw_init()
4513 	adev->gfx.mec.num_queue_per_pipe = 8;  in gfx_v7_0_sw_init()
4565 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {  in gfx_v7_0_sw_init()
4566 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {  in gfx_v7_0_sw_init()
4567 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {  in gfx_v7_0_sw_init()