Lines Matching refs:gfx
929 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
932 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
937 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
940 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
945 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
948 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
953 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
956 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
962 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
965 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()
971 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
974 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); in gfx_v7_0_init_microcode()
979 release_firmware(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
980 adev->gfx.pfp_fw = NULL; in gfx_v7_0_init_microcode()
981 release_firmware(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
982 adev->gfx.me_fw = NULL; in gfx_v7_0_init_microcode()
983 release_firmware(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
984 adev->gfx.ce_fw = NULL; in gfx_v7_0_init_microcode()
985 release_firmware(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
986 adev->gfx.mec_fw = NULL; in gfx_v7_0_init_microcode()
987 release_firmware(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()
988 adev->gfx.mec2_fw = NULL; in gfx_v7_0_init_microcode()
989 release_firmware(adev->gfx.rlc_fw); in gfx_v7_0_init_microcode()
990 adev->gfx.rlc_fw = NULL; in gfx_v7_0_init_microcode()
997 release_firmware(adev->gfx.pfp_fw); in gfx_v7_0_free_microcode()
998 adev->gfx.pfp_fw = NULL; in gfx_v7_0_free_microcode()
999 release_firmware(adev->gfx.me_fw); in gfx_v7_0_free_microcode()
1000 adev->gfx.me_fw = NULL; in gfx_v7_0_free_microcode()
1001 release_firmware(adev->gfx.ce_fw); in gfx_v7_0_free_microcode()
1002 adev->gfx.ce_fw = NULL; in gfx_v7_0_free_microcode()
1003 release_firmware(adev->gfx.mec_fw); in gfx_v7_0_free_microcode()
1004 adev->gfx.mec_fw = NULL; in gfx_v7_0_free_microcode()
1005 release_firmware(adev->gfx.mec2_fw); in gfx_v7_0_free_microcode()
1006 adev->gfx.mec2_fw = NULL; in gfx_v7_0_free_microcode()
1007 release_firmware(adev->gfx.rlc_fw); in gfx_v7_0_free_microcode()
1008 adev->gfx.rlc_fw = NULL; in gfx_v7_0_free_microcode()
1025 ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v7_0_tiling_mode_table_init()
1027 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in gfx_v7_0_tiling_mode_table_init()
1031 tile = adev->gfx.config.tile_mode_array; in gfx_v7_0_tiling_mode_table_init()
1032 macrotile = adev->gfx.config.macrotile_mode_array; in gfx_v7_0_tiling_mode_table_init()
1034 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v7_0_tiling_mode_table_init()
1630 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v7_0_get_rb_active_bitmap()
1631 adev->gfx.config.max_sh_per_se); in gfx_v7_0_get_rb_active_bitmap()
1673 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v7_0_write_harvested_raster_configs()
1674 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v7_0_write_harvested_raster_configs()
1792 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v7_0_setup_rb()
1793 adev->gfx.config.max_sh_per_se; in gfx_v7_0_setup_rb()
1797 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_setup_rb()
1798 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1801 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v7_0_setup_rb()
1807 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v7_0_setup_rb()
1808 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v7_0_setup_rb()
1810 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v7_0_setup_rb()
1811 adev->gfx.config.max_shader_engines, 16); in gfx_v7_0_setup_rb()
1815 if (!adev->gfx.config.backend_enable_mask || in gfx_v7_0_setup_rb()
1816 adev->gfx.config.num_rbs >= num_rb_pipes) { in gfx_v7_0_setup_rb()
1821 adev->gfx.config.backend_enable_mask, in gfx_v7_0_setup_rb()
1826 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_setup_rb()
1827 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1829 adev->gfx.config.rb_config[i][j].rb_backend_disable = in gfx_v7_0_setup_rb()
1831 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = in gfx_v7_0_setup_rb()
1833 adev->gfx.config.rb_config[i][j].raster_config = in gfx_v7_0_setup_rb()
1835 adev->gfx.config.rb_config[i][j].raster_config_1 = in gfx_v7_0_setup_rb()
1885 adev->gfx.config.double_offchip_lds_buf = 1; in gfx_v7_0_config_init()
1904 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v7_0_gpu_init()
1905 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v7_0_gpu_init()
1906 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); in gfx_v7_0_gpu_init()
1989 …((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIF… in gfx_v7_0_gpu_init()
1990 …(adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | in gfx_v7_0_gpu_init()
1991 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | in gfx_v7_0_gpu_init()
1992 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); in gfx_v7_0_gpu_init()
2042 adev->gfx.scratch.num_reg = 8; in gfx_v7_0_scratch_init()
2043 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v7_0_scratch_init()
2044 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v7_0_scratch_init()
2405 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_cp_gfx_enable()
2406 adev->gfx.gfx_ring[i].ready = false; in gfx_v7_0_cp_gfx_enable()
2427 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v7_0_cp_gfx_load_microcode()
2430 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2431 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2432 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2437 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2438 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2439 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2440 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2441 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2442 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2448 (adev->gfx.pfp_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2454 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2458 (adev->gfx.ce_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2464 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2468 (adev->gfx.me_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2474 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2490 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_start()
2496 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v7_0_cp_gfx_start()
2522 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_cp_gfx_start()
2536 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); in gfx_v7_0_cp_gfx_start()
2537 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v7_0_cp_gfx_start()
2586 ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_resume()
2677 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_cp_compute_enable()
2678 adev->gfx.compute_ring[i].ready = false; in gfx_v7_0_cp_compute_enable()
2697 if (!adev->gfx.mec_fw) in gfx_v7_0_cp_compute_load_microcode()
2700 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v7_0_cp_compute_load_microcode()
2702 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); in gfx_v7_0_cp_compute_load_microcode()
2703 adev->gfx.mec_feature_version = le32_to_cpu( in gfx_v7_0_cp_compute_load_microcode()
2710 (adev->gfx.mec_fw->data + in gfx_v7_0_cp_compute_load_microcode()
2721 if (!adev->gfx.mec2_fw) in gfx_v7_0_cp_compute_load_microcode()
2724 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; in gfx_v7_0_cp_compute_load_microcode()
2726 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); in gfx_v7_0_cp_compute_load_microcode()
2727 adev->gfx.mec2_feature_version = le32_to_cpu( in gfx_v7_0_cp_compute_load_microcode()
2732 (adev->gfx.mec2_fw->data + in gfx_v7_0_cp_compute_load_microcode()
2756 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_fini()
2757 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_cp_compute_fini()
2765 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v7_0_mec_fini()
2774 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v7_0_mec_init()
2780 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec in gfx_v7_0_mec_init()
2785 &adev->gfx.mec.hpd_eop_obj, in gfx_v7_0_mec_init()
2786 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v7_0_mec_init()
2797 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v7_0_mec_init()
2798 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v7_0_mec_init()
2847 size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe) in gfx_v7_0_compute_pipe_init()
2851 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset; in gfx_v7_0_compute_pipe_init()
3046 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v7_0_compute_queue_init()
3092 for (i = 0; i < adev->gfx.mec.num_mec; i++) in gfx_v7_0_cp_compute_resume()
3093 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) in gfx_v7_0_cp_compute_resume()
3097 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()
3107 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()
3108 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_cp_compute_resume()
3273 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL); in gfx_v7_0_rlc_fini()
3274 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL); in gfx_v7_0_rlc_fini()
3275 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL); in gfx_v7_0_rlc_fini()
3289 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3290 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3293 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3294 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3298 adev->gfx.rlc.cs_data = ci_cs_data; in gfx_v7_0_rlc_init()
3299 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ in gfx_v7_0_rlc_init()
3300 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ in gfx_v7_0_rlc_init()
3302 src_ptr = adev->gfx.rlc.reg_list; in gfx_v7_0_rlc_init()
3303 dws = adev->gfx.rlc.reg_list_size; in gfx_v7_0_rlc_init()
3306 cs_data = adev->gfx.rlc.cs_data; in gfx_v7_0_rlc_init()
3312 &adev->gfx.rlc.save_restore_obj, in gfx_v7_0_rlc_init()
3313 &adev->gfx.rlc.save_restore_gpu_addr, in gfx_v7_0_rlc_init()
3314 (void **)&adev->gfx.rlc.sr_ptr); in gfx_v7_0_rlc_init()
3322 dst_ptr = adev->gfx.rlc.sr_ptr; in gfx_v7_0_rlc_init()
3323 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) in gfx_v7_0_rlc_init()
3325 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); in gfx_v7_0_rlc_init()
3326 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); in gfx_v7_0_rlc_init()
3331 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev); in gfx_v7_0_rlc_init()
3335 &adev->gfx.rlc.clear_state_obj, in gfx_v7_0_rlc_init()
3336 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v7_0_rlc_init()
3337 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v7_0_rlc_init()
3345 dst_ptr = adev->gfx.rlc.cs_ptr; in gfx_v7_0_rlc_init()
3347 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); in gfx_v7_0_rlc_init()
3348 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v7_0_rlc_init()
3351 if (adev->gfx.rlc.cp_table_size) { in gfx_v7_0_rlc_init()
3353 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, in gfx_v7_0_rlc_init()
3355 &adev->gfx.rlc.cp_table_obj, in gfx_v7_0_rlc_init()
3356 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v7_0_rlc_init()
3357 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v7_0_rlc_init()
3366 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); in gfx_v7_0_rlc_init()
3367 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); in gfx_v7_0_rlc_init()
3392 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_wait_for_rlc_serdes()
3393 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_wait_for_rlc_serdes()
3539 if (!adev->gfx.rlc_fw) in gfx_v7_0_rlc_resume()
3542 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; in gfx_v7_0_rlc_resume()
3544 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); in gfx_v7_0_rlc_resume()
3545 adev->gfx.rlc_feature_version = le32_to_cpu( in gfx_v7_0_rlc_resume()
3572 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gfx_v7_0_rlc_resume()
3577 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v7_0_rlc_resume()
3798 if (adev->gfx.rlc.cp_table_ptr == NULL) in gfx_v7_0_init_cp_pg_table()
3802 dst_ptr = adev->gfx.rlc.cp_table_ptr; in gfx_v7_0_init_cp_pg_table()
3806 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v7_0_init_cp_pg_table()
3808 (adev->gfx.ce_fw->data + in gfx_v7_0_init_cp_pg_table()
3814 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v7_0_init_cp_pg_table()
3816 (adev->gfx.pfp_fw->data + in gfx_v7_0_init_cp_pg_table()
3822 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v7_0_init_cp_pg_table()
3824 (adev->gfx.me_fw->data + in gfx_v7_0_init_cp_pg_table()
3830 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v7_0_init_cp_pg_table()
3832 (adev->gfx.mec_fw->data + in gfx_v7_0_init_cp_pg_table()
3838 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; in gfx_v7_0_init_cp_pg_table()
3840 (adev->gfx.mec2_fw->data + in gfx_v7_0_init_cp_pg_table()
3909 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v7_0_get_cu_active_bitmap()
3918 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); in gfx_v7_0_init_ao_cu_mask()
3922 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); in gfx_v7_0_init_ao_cu_mask()
3962 if (adev->gfx.rlc.cs_data) { in gfx_v7_0_init_gfx_cgpg()
3964 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3965 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3966 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); in gfx_v7_0_init_gfx_cgpg()
3972 if (adev->gfx.rlc.reg_list) { in gfx_v7_0_init_gfx_cgpg()
3974 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) in gfx_v7_0_init_gfx_cgpg()
3975 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); in gfx_v7_0_init_gfx_cgpg()
3983 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v7_0_init_gfx_cgpg()
3984 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v7_0_init_gfx_cgpg()
4019 if (adev->gfx.rlc.cs_data == NULL) in gfx_v7_0_get_csb_size()
4027 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_get_csb_size()
4052 if (adev->gfx.rlc.cs_data == NULL) in gfx_v7_0_get_csb_buffer()
4064 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_get_csb_buffer()
4159 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v7_0_get_gpu_clock_counter()
4163 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v7_0_get_gpu_clock_counter()
4296 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; in gfx_v7_0_early_init()
4297 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; in gfx_v7_0_early_init()
4298 adev->gfx.funcs = &gfx_v7_0_gfx_funcs; in gfx_v7_0_early_init()
4299 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs; in gfx_v7_0_early_init()
4312 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v7_0_late_init()
4316 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v7_0_late_init()
4332 adev->gfx.config.max_shader_engines = 2; in gfx_v7_0_gpu_early_init()
4333 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()
4334 adev->gfx.config.max_cu_per_sh = 7; in gfx_v7_0_gpu_early_init()
4335 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4336 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()
4337 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v7_0_gpu_early_init()
4338 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4339 adev->gfx.config.max_gs_threads = 32; in gfx_v7_0_gpu_early_init()
4340 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4342 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4343 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4344 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4345 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4349 adev->gfx.config.max_shader_engines = 4; in gfx_v7_0_gpu_early_init()
4350 adev->gfx.config.max_tile_pipes = 16; in gfx_v7_0_gpu_early_init()
4351 adev->gfx.config.max_cu_per_sh = 11; in gfx_v7_0_gpu_early_init()
4352 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4353 adev->gfx.config.max_backends_per_se = 4; in gfx_v7_0_gpu_early_init()
4354 adev->gfx.config.max_texture_channel_caches = 16; in gfx_v7_0_gpu_early_init()
4355 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4356 adev->gfx.config.max_gs_threads = 32; in gfx_v7_0_gpu_early_init()
4357 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4359 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4360 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4361 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4362 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4366 adev->gfx.config.max_shader_engines = 1; in gfx_v7_0_gpu_early_init()
4367 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()
4368 adev->gfx.config.max_cu_per_sh = 8; in gfx_v7_0_gpu_early_init()
4369 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()
4370 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4371 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v7_0_gpu_early_init()
4372 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4373 adev->gfx.config.max_gs_threads = 16; in gfx_v7_0_gpu_early_init()
4374 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4376 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4377 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4378 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4379 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4385 adev->gfx.config.max_shader_engines = 1; in gfx_v7_0_gpu_early_init()
4386 adev->gfx.config.max_tile_pipes = 2; in gfx_v7_0_gpu_early_init()
4387 adev->gfx.config.max_cu_per_sh = 2; in gfx_v7_0_gpu_early_init()
4388 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4389 adev->gfx.config.max_backends_per_se = 1; in gfx_v7_0_gpu_early_init()
4390 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v7_0_gpu_early_init()
4391 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4392 adev->gfx.config.max_gs_threads = 16; in gfx_v7_0_gpu_early_init()
4393 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4395 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4396 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4397 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4398 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4404 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v7_0_gpu_early_init()
4405 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; in gfx_v7_0_gpu_early_init()
4407 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v7_0_gpu_early_init()
4408 adev->gfx.config.mem_max_burst_length_bytes = 256; in gfx_v7_0_gpu_early_init()
4432 adev->gfx.config.mem_row_size_in_kb = 2; in gfx_v7_0_gpu_early_init()
4434 adev->gfx.config.mem_row_size_in_kb = 1; in gfx_v7_0_gpu_early_init()
4437 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in gfx_v7_0_gpu_early_init()
4438 if (adev->gfx.config.mem_row_size_in_kb > 4) in gfx_v7_0_gpu_early_init()
4439 adev->gfx.config.mem_row_size_in_kb = 4; in gfx_v7_0_gpu_early_init()
4442 adev->gfx.config.shader_engine_tile_size = 32; in gfx_v7_0_gpu_early_init()
4443 adev->gfx.config.num_gpus = 1; in gfx_v7_0_gpu_early_init()
4444 adev->gfx.config.multi_gpu_tile_size = 64; in gfx_v7_0_gpu_early_init()
4448 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v7_0_gpu_early_init()
4460 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v7_0_gpu_early_init()
4468 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v7_0_compute_ring_init()
4481 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v7_0_compute_ring_init()
4486 &adev->gfx.eop_irq, irq_type); in gfx_v7_0_compute_ring_init()
4502 adev->gfx.mec.num_mec = 2; in gfx_v7_0_sw_init()
4509 adev->gfx.mec.num_mec = 1; in gfx_v7_0_sw_init()
4512 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v7_0_sw_init()
4513 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v7_0_sw_init()
4516 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); in gfx_v7_0_sw_init()
4522 &adev->gfx.priv_reg_irq); in gfx_v7_0_sw_init()
4528 &adev->gfx.priv_inst_irq); in gfx_v7_0_sw_init()
4553 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v7_0_sw_init()
4554 ring = &adev->gfx.gfx_ring[i]; in gfx_v7_0_sw_init()
4558 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); in gfx_v7_0_sw_init()
4565 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v7_0_sw_init()
4566 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v7_0_sw_init()
4567 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v7_0_sw_init()
4601 adev->gfx.ce_ram_size = 0x8000; in gfx_v7_0_sw_init()
4617 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_sw_fini()
4618 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v7_0_sw_fini()
4619 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_sw_fini()
4620 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v7_0_sw_fini()
4625 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v7_0_sw_fini()
4626 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v7_0_sw_fini()
4627 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v7_0_sw_fini()
4628 if (adev->gfx.rlc.cp_table_size) { in gfx_v7_0_sw_fini()
4629 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v7_0_sw_fini()
4630 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v7_0_sw_fini()
4631 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v7_0_sw_fini()
4661 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v7_0_hw_fini()
4662 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v7_0_hw_fini()
4964 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v7_0_eop_irq()
4968 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_eop_irq()
4969 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_eop_irq()
5126 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_set_ring_funcs()
5127 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; in gfx_v7_0_set_ring_funcs()
5128 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_set_ring_funcs()
5129 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; in gfx_v7_0_set_ring_funcs()
5149 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v7_0_set_irq_funcs()
5150 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; in gfx_v7_0_set_irq_funcs()
5152 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v7_0_set_irq_funcs()
5153 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; in gfx_v7_0_set_irq_funcs()
5155 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v7_0_set_irq_funcs()
5156 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; in gfx_v7_0_set_irq_funcs()
5192 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v7_0_get_cu_info()
5199 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v7_0_get_cu_info()
5206 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_get_cu_info()
5207 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_get_cu_info()
5218 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v7_0_get_cu_info()