2052 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v6_0_cp_gfx_start()
2373 	amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL);  in gfx_v6_0_rlc_fini()
2374 	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);  in gfx_v6_0_rlc_fini()
2375 	amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);  in gfx_v6_0_rlc_fini()
2387 	adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;  in gfx_v6_0_rlc_init()
2388 	adev->gfx.rlc.reg_list_size =  in gfx_v6_0_rlc_init()
2391 	adev->gfx.rlc.cs_data = si_cs_data;  in gfx_v6_0_rlc_init()
2392 	src_ptr = adev->gfx.rlc.reg_list;  in gfx_v6_0_rlc_init()
2393 	dws = adev->gfx.rlc.reg_list_size;  in gfx_v6_0_rlc_init()
2394 	cs_data = adev->gfx.rlc.cs_data;  in gfx_v6_0_rlc_init()
2400 					      &adev->gfx.rlc.save_restore_obj,  in gfx_v6_0_rlc_init()
2401 					      &adev->gfx.rlc.save_restore_gpu_addr,  in gfx_v6_0_rlc_init()
2402 					      (void **)&adev->gfx.rlc.sr_ptr);  in gfx_v6_0_rlc_init()
2411 		dst_ptr = adev->gfx.rlc.sr_ptr;  in gfx_v6_0_rlc_init()
2412 		for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)  in gfx_v6_0_rlc_init()
2415 		amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);  in gfx_v6_0_rlc_init()
2416 		amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);  in gfx_v6_0_rlc_init()
2421 		adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);  in gfx_v6_0_rlc_init()
2422 		dws = adev->gfx.rlc.clear_state_size + (256 / 4);  in gfx_v6_0_rlc_init()
2426 					      &adev->gfx.rlc.clear_state_obj,  in gfx_v6_0_rlc_init()
2427 					      &adev->gfx.rlc.clear_state_gpu_addr,  in gfx_v6_0_rlc_init()
2428 					      (void **)&adev->gfx.rlc.cs_ptr);  in gfx_v6_0_rlc_init()
2436 		dst_ptr = adev->gfx.rlc.cs_ptr;  in gfx_v6_0_rlc_init()
2437 		reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;  in gfx_v6_0_rlc_init()
2440 		dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);  in gfx_v6_0_rlc_init()
2442 		amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);  in gfx_v6_0_rlc_init()
2443 		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);  in gfx_v6_0_rlc_init()
2476 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)  in gfx_v6_0_update_rlc()  argument
2481 	if (tmp != rlc)  in gfx_v6_0_update_rlc()
2482 		WREG32(mmRLC_CNTL, rlc);  in gfx_v6_0_update_rlc()
2847 	WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);  in gfx_v6_0_init_gfx_cgpg()
2849 	WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);  in gfx_v6_0_init_gfx_cgpg()
2871 	if (adev->gfx.rlc.cs_data == NULL)  in gfx_v6_0_get_csb_size()
2879 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v6_0_get_csb_size()
2904 	if (adev->gfx.rlc.cs_data == NULL)  in gfx_v6_0_get_csb_buffer()
2915 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v6_0_get_csb_buffer()
2955 			WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);  in gfx_v6_0_init_pg()
2956 			WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);  in gfx_v6_0_init_pg()
2963 		WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);  in gfx_v6_0_init_pg()
2964 		WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);  in gfx_v6_0_init_pg()