84 	uint32_t	hpd;  member
90 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
95 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
100 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
105 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
110 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
115 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
219 			       enum amdgpu_hpd_id hpd)  in dce_v8_0_hpd_sense()  argument
223 	if (hpd >= adev->mode_info.num_hpd)  in dce_v8_0_hpd_sense()
226 	if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &  in dce_v8_0_hpd_sense()
242 				      enum amdgpu_hpd_id hpd)  in dce_v8_0_hpd_set_polarity()  argument
245 	bool connected = dce_v8_0_hpd_sense(adev, hpd);  in dce_v8_0_hpd_set_polarity()
247 	if (hpd >= adev->mode_info.num_hpd)  in dce_v8_0_hpd_set_polarity()
250 	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);  in dce_v8_0_hpd_set_polarity()
255 	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v8_0_hpd_set_polarity()
275 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v8_0_hpd_init()
278 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v8_0_hpd_init()
280 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v8_0_hpd_init()
289 			tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v8_0_hpd_init()
291 			WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v8_0_hpd_init()
295 		dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v8_0_hpd_init()
296 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v8_0_hpd_init()
317 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v8_0_hpd_fini()
320 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v8_0_hpd_fini()
322 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);  in dce_v8_0_hpd_fini()
324 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v8_0_hpd_fini()
3120 	unsigned hpd;  in dce_v8_0_hpd_irq()  local
3127 	hpd = entry->src_data[0];  in dce_v8_0_hpd_irq()
3128 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v8_0_hpd_irq()
3129 	mask = interrupt_status_offsets[hpd].hpd;  in dce_v8_0_hpd_irq()
3132 		tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);  in dce_v8_0_hpd_irq()
3134 		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v8_0_hpd_irq()
3136 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);  in dce_v8_0_hpd_irq()