85 	uint32_t	hpd;  member
91 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
96 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
101 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
106 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
111 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
116 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
224 			       enum amdgpu_hpd_id hpd)  in dce_v6_0_hpd_sense()  argument
228 	if (hpd >= adev->mode_info.num_hpd)  in dce_v6_0_hpd_sense()
231 	if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)  in dce_v6_0_hpd_sense()
246 				      enum amdgpu_hpd_id hpd)  in dce_v6_0_hpd_set_polarity()  argument
249 	bool connected = dce_v6_0_hpd_sense(adev, hpd);  in dce_v6_0_hpd_set_polarity()
251 	if (hpd >= adev->mode_info.num_hpd)  in dce_v6_0_hpd_set_polarity()
254 	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);  in dce_v6_0_hpd_set_polarity()
259 	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v6_0_hpd_set_polarity()
279 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v6_0_hpd_init()
282 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v6_0_hpd_init()
284 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v6_0_hpd_init()
293 			tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v6_0_hpd_init()
295 			WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v6_0_hpd_init()
299 		dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v6_0_hpd_init()
300 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v6_0_hpd_init()
322 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v6_0_hpd_fini()
325 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v6_0_hpd_fini()
327 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);  in dce_v6_0_hpd_fini()
329 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v6_0_hpd_fini()
3025 	unsigned hpd;  in dce_v6_0_hpd_irq()  local
3032 	hpd = entry->src_data[0];  in dce_v6_0_hpd_irq()
3033 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v6_0_hpd_irq()
3034 	mask = interrupt_status_offsets[hpd].hpd;  in dce_v6_0_hpd_irq()
3037 		tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);  in dce_v6_0_hpd_irq()
3039 		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v6_0_hpd_irq()
3041 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);  in dce_v6_0_hpd_irq()