86 	uint32_t        hpd;  member
92 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
97 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
102 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
107 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
112 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
117 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
292 			       enum amdgpu_hpd_id hpd)  in dce_v11_0_hpd_sense()  argument
296 	if (hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_sense()
299 	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &  in dce_v11_0_hpd_sense()
315 				      enum amdgpu_hpd_id hpd)  in dce_v11_0_hpd_set_polarity()  argument
318 	bool connected = dce_v11_0_hpd_sense(adev, hpd);  in dce_v11_0_hpd_set_polarity()
320 	if (hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_set_polarity()
323 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_hpd_set_polarity()
328 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_hpd_set_polarity()
348 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_init()
358 			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_init()
360 			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_init()
364 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_init()
366 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_init()
368 		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_init()
375 		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_init()
377 		dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_init()
378 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_init()
399 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_fini()
402 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_fini()
404 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_fini()
406 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_fini()
3119 					unsigned hpd,  in dce_v11_0_set_hpd_irq_state()  argument
3124 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v11_0_set_hpd_irq_state()
3125 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v11_0_set_hpd_irq_state()
3131 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_set_hpd_irq_state()
3133 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_set_hpd_irq_state()
3136 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_set_hpd_irq_state()
3138 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_set_hpd_irq_state()
3272 				  int hpd)  in dce_v11_0_hpd_int_ack()  argument
3276 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v11_0_hpd_int_ack()
3277 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v11_0_hpd_int_ack()
3281 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_hpd_int_ack()
3283 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_hpd_int_ack()
3360 	unsigned hpd;  in dce_v11_0_hpd_irq()  local
3367 	hpd = entry->src_data[0];  in dce_v11_0_hpd_irq()
3368 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v11_0_hpd_irq()
3369 	mask = interrupt_status_offsets[hpd].hpd;  in dce_v11_0_hpd_irq()
3372 		dce_v11_0_hpd_int_ack(adev, hpd);  in dce_v11_0_hpd_irq()
3374 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);  in dce_v11_0_hpd_irq()