84 	uint32_t        hpd;  member
90 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
95 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
100 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
105 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
110 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
115 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
274 			       enum amdgpu_hpd_id hpd)  in dce_v10_0_hpd_sense()  argument
278 	if (hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_sense()
281 	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &  in dce_v10_0_hpd_sense()
297 				      enum amdgpu_hpd_id hpd)  in dce_v10_0_hpd_set_polarity()  argument
300 	bool connected = dce_v10_0_hpd_sense(adev, hpd);  in dce_v10_0_hpd_set_polarity()
302 	if (hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_set_polarity()
305 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_hpd_set_polarity()
310 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_hpd_set_polarity()
330 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_init()
340 			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_init()
342 			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_init()
346 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_init()
348 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_init()
350 		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_init()
357 		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_init()
359 		dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_init()
361 			       amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_init()
382 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_fini()
385 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_fini()
387 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_fini()
390 			       amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_fini()
2993 				       unsigned hpd,  in dce_v10_0_set_hpd_irq_state()  argument
2998 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v10_0_set_hpd_irq_state()
2999 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v10_0_set_hpd_irq_state()
3005 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_set_hpd_irq_state()
3007 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_set_hpd_irq_state()
3010 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_set_hpd_irq_state()
3012 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_set_hpd_irq_state()
3146 				  int hpd)  in dce_v10_0_hpd_int_ack()  argument
3150 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v10_0_hpd_int_ack()
3151 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v10_0_hpd_int_ack()
3155 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_hpd_int_ack()
3157 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_hpd_int_ack()
3233 	unsigned hpd;  in dce_v10_0_hpd_irq()  local
3240 	hpd = entry->src_data[0];  in dce_v10_0_hpd_irq()
3241 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v10_0_hpd_irq()
3242 	mask = interrupt_status_offsets[hpd].hpd;  in dce_v10_0_hpd_irq()
3245 		dce_v10_0_hpd_int_ack(adev, hpd);  in dce_v10_0_hpd_irq()
3247 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);  in dce_v10_0_hpd_irq()