1200 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;  in dce_v10_0_afmt_audio_select_pin()  local
1203 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v10_0_afmt_audio_select_pin()
1206 	tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_audio_select_pin()
1207 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);  in dce_v10_0_afmt_audio_select_pin()
1208 	WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_audio_select_pin()
1216 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;  in dce_v10_0_audio_write_latency_fields()  local
1222 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v10_0_audio_write_latency_fields()
1250 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v10_0_audio_write_latency_fields()
1258 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;  in dce_v10_0_audio_write_speaker_allocation()  local
1265 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v10_0_audio_write_speaker_allocation()
1287 	tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v10_0_audio_write_speaker_allocation()
1300 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v10_0_audio_write_speaker_allocation()
1310 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;  in dce_v10_0_audio_write_sad_regs()  local
1331 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v10_0_audio_write_sad_regs()
1382 		WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);  in dce_v10_0_audio_write_sad_regs()
1463 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;  in dce_v10_0_afmt_update_ACR()  local
1466 	tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1468 	WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1469 	tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1471 	WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1473 	tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1475 	WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1476 	tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1478 	WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1480 	tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1482 	WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1483 	tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1485 	WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1498 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;  in dce_v10_0_afmt_update_avi_infoframe()  local
1502 	WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,  in dce_v10_0_afmt_update_avi_infoframe()
1504 	WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,  in dce_v10_0_afmt_update_avi_infoframe()
1506 	WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,  in dce_v10_0_afmt_update_avi_infoframe()
1508 	WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,  in dce_v10_0_afmt_update_avi_infoframe()
1517 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;  in dce_v10_0_audio_set_dto()  local
1523 	if (!dig || !dig->afmt)  in dce_v10_0_audio_set_dto()
1548 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;  in dce_v10_0_afmt_setmode()  local
1556 	if (!dig || !dig->afmt)  in dce_v10_0_afmt_setmode()
1560 	if (!dig->afmt->enabled)  in dce_v10_0_afmt_setmode()
1570 	dig->afmt->pin = dce_v10_0_audio_get_pin(adev);  in dce_v10_0_afmt_setmode()
1571 	dce_v10_0_audio_enable(adev, dig->afmt->pin, false);  in dce_v10_0_afmt_setmode()
1575 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1577 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */  in dce_v10_0_afmt_setmode()
1579 	WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);  in dce_v10_0_afmt_setmode()
1581 	tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1606 	WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1608 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1612 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1614 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1619 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1621 	tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1624 	WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1626 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1629 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1631 	WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */  in dce_v10_0_afmt_setmode()
1633 	tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1638 	WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1640 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1643 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1645 	tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1654 	WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1658 	tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1660 	WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1662 	tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1664 	WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1666 	tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1673 	WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1677 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,  in dce_v10_0_afmt_setmode()
1698 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1703 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1705 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1707 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1709 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1712 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1714 	WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);  in dce_v10_0_afmt_setmode()
1715 	WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);  in dce_v10_0_afmt_setmode()
1716 	WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);  in dce_v10_0_afmt_setmode()
1717 	WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);  in dce_v10_0_afmt_setmode()
1720 	dce_v10_0_audio_enable(adev, dig->afmt->pin, true);  in dce_v10_0_afmt_setmode()
1728 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;  in dce_v10_0_afmt_enable()  local
1730 	if (!dig || !dig->afmt)  in dce_v10_0_afmt_enable()
1734 	if (enable && dig->afmt->enabled)  in dce_v10_0_afmt_enable()
1736 	if (!enable && !dig->afmt->enabled)  in dce_v10_0_afmt_enable()
1739 	if (!enable && dig->afmt->pin) {  in dce_v10_0_afmt_enable()
1740 		dce_v10_0_audio_enable(adev, dig->afmt->pin, false);  in dce_v10_0_afmt_enable()
1741 		dig->afmt->pin = NULL;  in dce_v10_0_afmt_enable()
1744 	dig->afmt->enabled = enable;  in dce_v10_0_afmt_enable()
1747 		  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);  in dce_v10_0_afmt_enable()
2160 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;  in dce_v10_0_pick_dig_encoder()  local
2164 		if (dig->linkb)  in dce_v10_0_pick_dig_encoder()
2170 		if (dig->linkb)  in dce_v10_0_pick_dig_encoder()
2176 		if (dig->linkb)  in dce_v10_0_pick_dig_encoder()
3314 		struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;  in dce_v10_0_encoder_prepare()  local
3315 		if (dig) {  in dce_v10_0_encoder_prepare()
3316 			dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);  in dce_v10_0_encoder_prepare()
3318 				dig->afmt = adev->mode_info.afmt[dig->dig_encoder];  in dce_v10_0_encoder_prepare()
3356 	struct amdgpu_encoder_atom_dig *dig;  in dce_v10_0_encoder_disable()  local
3363 		dig = amdgpu_encoder->enc_priv;  in dce_v10_0_encoder_disable()
3364 		dig->dig_encoder = -1;  in dce_v10_0_encoder_disable()