326 static struct ci_ps *ci_get_ps(struct amdgpu_ps *rps)  in ci_get_ps()  argument
328 	struct ci_ps *ps = rps->ps_priv;  in ci_get_ps()
926 					struct amdgpu_ps *rps)  in ci_apply_state_adjust_rules()  argument
928 	struct ci_ps *ps = ci_get_ps(rps);  in ci_apply_state_adjust_rules()
935 	if (rps->vce_active) {  in ci_apply_state_adjust_rules()
936 		rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;  in ci_apply_state_adjust_rules()
937 		rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;  in ci_apply_state_adjust_rules()
939 		rps->evclk = 0;  in ci_apply_state_adjust_rules()
940 		rps->ecclk = 0;  in ci_apply_state_adjust_rules()
949 	if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)  in ci_apply_state_adjust_rules()
984 	if (rps->vce_active) {  in ci_apply_state_adjust_rules()
5240 				 struct amdgpu_ps *rps)  in ci_update_current_ps()  argument
5242 	struct ci_ps *new_ps = ci_get_ps(rps);  in ci_update_current_ps()
5245 	pi->current_rps = *rps;  in ci_update_current_ps()
5252 				   struct amdgpu_ps *rps)  in ci_update_requested_ps()  argument
5254 	struct ci_ps *new_ps = ci_get_ps(rps);  in ci_update_requested_ps()
5257 	pi->requested_rps = *rps;  in ci_update_requested_ps()
5557 					  struct amdgpu_ps *rps,  in ci_parse_pplib_non_clock_info()  argument
5561 	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);  in ci_parse_pplib_non_clock_info()
5562 	rps->class = le16_to_cpu(non_clock_info->usClassification);  in ci_parse_pplib_non_clock_info()
5563 	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);  in ci_parse_pplib_non_clock_info()
5566 		rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);  in ci_parse_pplib_non_clock_info()
5567 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);  in ci_parse_pplib_non_clock_info()
5569 		rps->vclk = 0;  in ci_parse_pplib_non_clock_info()
5570 		rps->dclk = 0;  in ci_parse_pplib_non_clock_info()
5573 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)  in ci_parse_pplib_non_clock_info()
5574 		adev->pm.dpm.boot_ps = rps;  in ci_parse_pplib_non_clock_info()
5575 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)  in ci_parse_pplib_non_clock_info()
5576 		adev->pm.dpm.uvd_ps = rps;  in ci_parse_pplib_non_clock_info()
5580 				      struct amdgpu_ps *rps, int index,  in ci_parse_pplib_clock_info()  argument
5584 	struct ci_ps *ps = ci_get_ps(rps);  in ci_parse_pplib_clock_info()
5602 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {  in ci_parse_pplib_clock_info()
5606 	if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {  in ci_parse_pplib_clock_info()
5613 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {  in ci_parse_pplib_clock_info()
5620 	switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {  in ci_parse_pplib_clock_info()
6089 	struct amdgpu_ps *rps = &pi->current_rps;  in ci_dpm_debugfs_print_current_performance_level()  local
6105 	seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");  in ci_dpm_debugfs_print_current_performance_level()
6113 	struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;  in ci_dpm_print_power_state()  local
6114 	struct ci_ps *ps = ci_get_ps(rps);  in ci_dpm_print_power_state()
6119 	amdgpu_dpm_print_class_info(rps->class, rps->class2);  in ci_dpm_print_power_state()
6120 	amdgpu_dpm_print_cap_info(rps->caps);  in ci_dpm_print_power_state()
6121 	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);  in ci_dpm_print_power_state()
6127 	amdgpu_dpm_print_ps_status(adev, rps);  in ci_dpm_print_power_state()
6148 	struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;  in ci_check_state_equal()  local
6151 	if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)  in ci_check_state_equal()
6155 	ci_rps = ci_get_ps((struct amdgpu_ps *)rps);  in ci_check_state_equal()
6177 	*equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));  in ci_check_state_equal()
6178 	*equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));  in ci_check_state_equal()