Lines Matching refs:pi
321 struct ci_power_info *pi = adev->pm.dpm.priv; in ci_get_pi() local
323 return pi; in ci_get_pi()
335 struct ci_power_info *pi = ci_get_pi(adev); in ci_initialize_powertune_defaults() local
345 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
351 pi->powertune_defaults = &defaults_saturn_xt; in ci_initialize_powertune_defaults()
355 pi->powertune_defaults = &defaults_hawaii_xt; in ci_initialize_powertune_defaults()
359 pi->powertune_defaults = &defaults_hawaii_pro; in ci_initialize_powertune_defaults()
369 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
373 pi->dte_tj_offset = 0; in ci_initialize_powertune_defaults()
375 pi->caps_power_containment = true; in ci_initialize_powertune_defaults()
376 pi->caps_cac = false; in ci_initialize_powertune_defaults()
377 pi->caps_sq_ramping = false; in ci_initialize_powertune_defaults()
378 pi->caps_db_ramping = false; in ci_initialize_powertune_defaults()
379 pi->caps_td_ramping = false; in ci_initialize_powertune_defaults()
380 pi->caps_tcp_ramping = false; in ci_initialize_powertune_defaults()
382 if (pi->caps_power_containment) { in ci_initialize_powertune_defaults()
383 pi->caps_cac = true; in ci_initialize_powertune_defaults()
385 pi->enable_bapm_feature = false; in ci_initialize_powertune_defaults()
387 pi->enable_bapm_feature = true; in ci_initialize_powertune_defaults()
388 pi->enable_tdc_limit_feature = true; in ci_initialize_powertune_defaults()
389 pi->enable_pkg_pwr_tracking_feature = true; in ci_initialize_powertune_defaults()
400 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_bapm_vddc_vid_sidd() local
401 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_populate_bapm_vddc_vid_sidd()
402 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_populate_bapm_vddc_vid_sidd()
403 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; in ci_populate_bapm_vddc_vid_sidd()
429 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_vddc_vid() local
430 u8 *vid = pi->smc_powertune_table.VddCVid; in ci_populate_vddc_vid()
433 if (pi->vddc_voltage_table.count > 8) in ci_populate_vddc_vid()
436 for (i = 0; i < pi->vddc_voltage_table.count; i++) in ci_populate_vddc_vid()
437 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); in ci_populate_vddc_vid()
444 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_svi_load_line() local
445 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_svi_load_line()
447 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; in ci_populate_svi_load_line()
448 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; in ci_populate_svi_load_line()
449 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; in ci_populate_svi_load_line()
450 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; in ci_populate_svi_load_line()
457 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_tdc_limit() local
458 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_tdc_limit()
462 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); in ci_populate_tdc_limit()
463 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = in ci_populate_tdc_limit()
465 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; in ci_populate_tdc_limit()
472 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_dw8() local
473 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_dw8()
480 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, in ci_populate_dw8()
481 pi->sram_end); in ci_populate_dw8()
485 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; in ci_populate_dw8()
492 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_fuzzy_fan() local
499 pi->smc_powertune_table.FuzzyFan_PwmSetDelta = in ci_populate_fuzzy_fan()
507 struct ci_power_info *pi = ci_get_pi(adev); in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc() local
508 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
509 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
531 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
532 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
539 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_bapm_vddc_base_leakage_sidd() local
540 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd; in ci_populate_bapm_vddc_base_leakage_sidd()
541 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd; in ci_populate_bapm_vddc_base_leakage_sidd()
548 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
549 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
556 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_bapm_parameters_in_dpm_table() local
557 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_bapm_parameters_in_dpm_table()
558 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table()
569 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
571 (u8)(pi->thermal_temp_setting.temperature_high / 1000); in ci_populate_bapm_parameters_in_dpm_table()
604 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_pm_base() local
608 if (pi->caps_power_containment) { in ci_populate_pm_base()
612 &pm_fuse_table_offset, pi->sram_end); in ci_populate_pm_base()
640 (u8 *)&pi->smc_powertune_table, in ci_populate_pm_base()
641 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); in ci_populate_pm_base()
651 struct ci_power_info *pi = ci_get_pi(adev); in ci_do_enable_didt() local
654 if (pi->caps_sq_ramping) { in ci_do_enable_didt()
663 if (pi->caps_db_ramping) { in ci_do_enable_didt()
672 if (pi->caps_td_ramping) { in ci_do_enable_didt()
681 if (pi->caps_tcp_ramping) { in ci_do_enable_didt()
741 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_didt() local
744 if (pi->caps_sq_ramping || pi->caps_db_ramping || in ci_enable_didt()
745 pi->caps_td_ramping || pi->caps_tcp_ramping) { in ci_enable_didt()
766 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_power_containment() local
771 pi->power_containment_features = 0; in ci_enable_power_containment()
772 if (pi->caps_power_containment) { in ci_enable_power_containment()
773 if (pi->enable_bapm_feature) { in ci_enable_power_containment()
778 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; in ci_enable_power_containment()
781 if (pi->enable_tdc_limit_feature) { in ci_enable_power_containment()
786 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; in ci_enable_power_containment()
789 if (pi->enable_pkg_pwr_tracking_feature) { in ci_enable_power_containment()
799 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; in ci_enable_power_containment()
806 if (pi->caps_power_containment && pi->power_containment_features) { in ci_enable_power_containment()
807 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) in ci_enable_power_containment()
810 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) in ci_enable_power_containment()
813 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) in ci_enable_power_containment()
815 pi->power_containment_features = 0; in ci_enable_power_containment()
824 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_smc_cac() local
828 if (pi->caps_cac) { in ci_enable_smc_cac()
833 pi->cac_enabled = false; in ci_enable_smc_cac()
835 pi->cac_enabled = true; in ci_enable_smc_cac()
837 } else if (pi->cac_enabled) { in ci_enable_smc_cac()
839 pi->cac_enabled = false; in ci_enable_smc_cac()
849 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_thermal_based_sclk_dpm() local
852 if (pi->thermal_sclk_dpm_enabled) { in ci_enable_thermal_based_sclk_dpm()
867 struct ci_power_info *pi = ci_get_pi(adev); in ci_power_control_set_level() local
875 if (pi->caps_power_containment) { in ci_power_control_set_level()
890 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_powergate_uvd() local
892 pi->uvd_power_gated = gate; in ci_dpm_powergate_uvd()
929 struct ci_power_info *pi = ci_get_pi(adev); in ci_apply_state_adjust_rules() local
950 pi->battery_state = true; in ci_apply_state_adjust_rules()
952 pi->battery_state = false; in ci_apply_state_adjust_rules()
1072 struct ci_power_info *pi = ci_get_pi(adev); in ci_fan_ctrl_set_static_mode() local
1075 if (pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_static_mode()
1078 pi->fan_ctrl_default_mode = tmp; in ci_fan_ctrl_set_static_mode()
1081 pi->t_min = tmp; in ci_fan_ctrl_set_static_mode()
1082 pi->fan_ctrl_is_in_default_mode = false; in ci_fan_ctrl_set_static_mode()
1096 struct ci_power_info *pi = ci_get_pi(adev); in ci_thermal_setup_fan_table() local
1105 if (!pi->fan_table_start) { in ci_thermal_setup_fan_table()
1160 pi->fan_table_start, in ci_thermal_setup_fan_table()
1163 pi->sram_end); in ci_thermal_setup_fan_table()
1175 struct ci_power_info *pi = ci_get_pi(adev); in ci_fan_ctrl_start_smc_fan_control() local
1178 if (pi->caps_od_fuzzy_fan_control_support) { in ci_fan_ctrl_start_smc_fan_control()
1197 pi->fan_is_controlled_by_smc = true; in ci_fan_ctrl_start_smc_fan_control()
1205 struct ci_power_info *pi = ci_get_pi(adev); in ci_fan_ctrl_stop_smc_fan_control() local
1209 pi->fan_is_controlled_by_smc = false; in ci_fan_ctrl_stop_smc_fan_control()
1251 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_set_fan_speed_percent() local
1256 if (pi->fan_is_controlled_by_smc) in ci_dpm_set_fan_speed_percent()
1305 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_get_fan_control_mode() local
1307 if (pi->fan_is_controlled_by_smc) in ci_dpm_get_fan_control_mode()
1368 struct ci_power_info *pi = ci_get_pi(adev); in ci_fan_ctrl_set_default_mode() local
1371 if (!pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_default_mode()
1373 tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; in ci_fan_ctrl_set_default_mode()
1377 tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT; in ci_fan_ctrl_set_default_mode()
1379 pi->fan_ctrl_is_in_default_mode = true; in ci_fan_ctrl_set_default_mode()
1437 struct ci_power_info *pi = ci_get_pi(adev); in ci_read_smc_soft_register() local
1440 pi->soft_regs_start + reg_offset, in ci_read_smc_soft_register()
1441 value, pi->sram_end); in ci_read_smc_soft_register()
1447 struct ci_power_info *pi = ci_get_pi(adev); in ci_write_smc_soft_register() local
1450 pi->soft_regs_start + reg_offset, in ci_write_smc_soft_register()
1451 value, pi->sram_end); in ci_write_smc_soft_register()
1456 struct ci_power_info *pi = ci_get_pi(adev); in ci_init_fps_limits() local
1457 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits()
1459 if (pi->caps_fps) { in ci_init_fps_limits()
1472 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_sclk_t() local
1476 if (pi->caps_sclk_throttle_low_notification) { in ci_update_sclk_t()
1477 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in ci_update_sclk_t()
1480 pi->dpm_table_start + in ci_update_sclk_t()
1483 sizeof(u32), pi->sram_end); in ci_update_sclk_t()
1492 struct ci_power_info *pi = ci_get_pi(adev); in ci_get_leakage_voltages() local
1497 pi->vddc_leakage.count = 0; in ci_get_leakage_voltages()
1498 pi->vddci_leakage.count = 0; in ci_get_leakage_voltages()
1506 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1507 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1508 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1518 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1519 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1520 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1523 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; in ci_get_leakage_voltages()
1524 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1525 pi->vddci_leakage.count++; in ci_get_leakage_voltages()
1534 struct ci_power_info *pi = ci_get_pi(adev); in ci_set_dpm_event_sources() local
1569 if (pi->thermal_protection) in ci_set_dpm_event_sources()
1585 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_auto_throttle_source() local
1588 if (!(pi->active_auto_throttle_sources & (1 << source))) { in ci_enable_auto_throttle_source()
1589 pi->active_auto_throttle_sources |= 1 << source; in ci_enable_auto_throttle_source()
1590 ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1593 if (pi->active_auto_throttle_sources & (1 << source)) { in ci_enable_auto_throttle_source()
1594 pi->active_auto_throttle_sources &= ~(1 << source); in ci_enable_auto_throttle_source()
1595 ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1608 struct ci_power_info *pi = ci_get_pi(adev); in ci_unfreeze_sclk_mclk_dpm() local
1611 if (!pi->need_update_smu7_dpm_table) in ci_unfreeze_sclk_mclk_dpm()
1614 if ((!pi->sclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1615 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_unfreeze_sclk_mclk_dpm()
1621 if ((!pi->mclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1622 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_unfreeze_sclk_mclk_dpm()
1628 pi->need_update_smu7_dpm_table = 0; in ci_unfreeze_sclk_mclk_dpm()
1634 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_sclk_mclk_dpm() local
1638 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1644 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1663 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1669 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1681 struct ci_power_info *pi = ci_get_pi(adev); in ci_start_dpm() local
1706 if (!pi->pcie_dpm_key_disabled) { in ci_start_dpm()
1717 struct ci_power_info *pi = ci_get_pi(adev); in ci_freeze_sclk_mclk_dpm() local
1720 if (!pi->need_update_smu7_dpm_table) in ci_freeze_sclk_mclk_dpm()
1723 if ((!pi->sclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1724 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_freeze_sclk_mclk_dpm()
1730 if ((!pi->mclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1731 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_freeze_sclk_mclk_dpm()
1742 struct ci_power_info *pi = ci_get_pi(adev); in ci_stop_dpm() local
1755 if (!pi->pcie_dpm_key_disabled) { in ci_stop_dpm()
1787 struct ci_power_info *pi = ci_get_pi(adev);
1799 if (pi->caps_automatic_dc_transition) {
1832 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_force_state_sclk() local
1834 if (!pi->sclk_dpm_key_disabled) { in ci_dpm_force_state_sclk()
1846 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_force_state_mclk() local
1848 if (!pi->mclk_dpm_key_disabled) { in ci_dpm_force_state_mclk()
1860 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_force_state_pcie() local
1862 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_state_pcie()
1874 struct ci_power_info *pi = ci_get_pi(adev); in ci_set_power_limit() local
1876 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { in ci_set_power_limit()
1950 struct ci_power_info *pi = ci_get_pi(adev); in ci_process_firmware_header() local
1957 &tmp, pi->sram_end); in ci_process_firmware_header()
1961 pi->dpm_table_start = tmp; in ci_process_firmware_header()
1966 &tmp, pi->sram_end); in ci_process_firmware_header()
1970 pi->soft_regs_start = tmp; in ci_process_firmware_header()
1975 &tmp, pi->sram_end); in ci_process_firmware_header()
1979 pi->mc_reg_table_start = tmp; in ci_process_firmware_header()
1984 &tmp, pi->sram_end); in ci_process_firmware_header()
1988 pi->fan_table_start = tmp; in ci_process_firmware_header()
1993 &tmp, pi->sram_end); in ci_process_firmware_header()
1997 pi->arb_table_start = tmp; in ci_process_firmware_header()
2004 struct ci_power_info *pi = ci_get_pi(adev); in ci_read_clock_registers() local
2006 pi->clock_registers.cg_spll_func_cntl = in ci_read_clock_registers()
2008 pi->clock_registers.cg_spll_func_cntl_2 = in ci_read_clock_registers()
2010 pi->clock_registers.cg_spll_func_cntl_3 = in ci_read_clock_registers()
2012 pi->clock_registers.cg_spll_func_cntl_4 = in ci_read_clock_registers()
2014 pi->clock_registers.cg_spll_spread_spectrum = in ci_read_clock_registers()
2016 pi->clock_registers.cg_spll_spread_spectrum_2 = in ci_read_clock_registers()
2018 pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL); in ci_read_clock_registers()
2019 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL); in ci_read_clock_registers()
2020 pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL); in ci_read_clock_registers()
2021 pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
2022 pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL); in ci_read_clock_registers()
2023 pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1); in ci_read_clock_registers()
2024 pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2); in ci_read_clock_registers()
2025 pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1); in ci_read_clock_registers()
2026 pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2); in ci_read_clock_registers()
2031 struct ci_power_info *pi = ci_get_pi(adev); in ci_init_sclk_t() local
2033 pi->low_sclk_interrupt_t = 0; in ci_init_sclk_t()
2097 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_ds_master_switch() local
2100 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
2108 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
2153 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_spread_spectrum() local
2157 if (pi->caps_sclk_ss_support) { in ci_enable_spread_spectrum()
2275 struct ci_power_info *pi = ci_get_pi(adev); in ci_construct_voltage_tables() local
2278 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2281 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2284 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2287 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2292 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) in ci_construct_voltage_tables()
2294 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2296 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2299 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2302 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2305 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2310 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) in ci_construct_voltage_tables()
2312 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2314 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2317 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2320 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2323 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2328 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) in ci_construct_voltage_tables()
2330 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2360 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_vddc_table() local
2363 table->VddcLevelCount = pi->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
2366 &pi->vddc_voltage_table.entries[count], in ci_populate_smc_vddc_table()
2369 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddc_table()
2371 pi->vddc_voltage_table.entries[count].smio_low; in ci_populate_smc_vddc_table()
2384 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_vddci_table() local
2386 table->VddciLevelCount = pi->vddci_voltage_table.count; in ci_populate_smc_vddci_table()
2389 &pi->vddci_voltage_table.entries[count], in ci_populate_smc_vddci_table()
2392 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddci_table()
2394 pi->vddci_voltage_table.entries[count].smio_low; in ci_populate_smc_vddci_table()
2406 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_mvdd_table() local
2409 table->MvddLevelCount = pi->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
2412 &pi->mvdd_voltage_table.entries[count], in ci_populate_smc_mvdd_table()
2415 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_mvdd_table()
2417 pi->mvdd_voltage_table.entries[count].smio_low; in ci_populate_smc_mvdd_table()
2449 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_mvdd_value() local
2452 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_mvdd_value()
2455 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; in ci_populate_mvdd_value()
2554 struct ci_power_info *pi = ci_get_pi(adev); in ci_init_arb_table_index() local
2558 ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start, in ci_init_arb_table_index()
2559 &tmp, pi->sram_end); in ci_init_arb_table_index()
2566 return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start, in ci_init_arb_table_index()
2567 tmp, pi->sram_end); in ci_init_arb_table_index()
2684 struct ci_power_info *pi = ci_get_pi(adev); in ci_do_program_memory_timing_parameters() local
2691 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2692 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2694 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2695 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2704 pi->arb_table_start, in ci_do_program_memory_timing_parameters()
2707 pi->sram_end); in ci_do_program_memory_timing_parameters()
2714 struct ci_power_info *pi = ci_get_pi(adev); in ci_program_memory_timing_parameters() local
2716 if (pi->need_update_smu7_dpm_table == 0) in ci_program_memory_timing_parameters()
2726 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_initial_state() local
2732 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()
2740 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()
2765 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_link_level() local
2766 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_smc_link_level()
2779 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
2780 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()
2930 struct ci_power_info *pi = ci_get_pi(adev); in ci_calculate_mclk_params() local
2931 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_calculate_mclk_params()
2932 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_calculate_mclk_params()
2933 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; in ci_calculate_mclk_params()
2934 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; in ci_calculate_mclk_params()
2935 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; in ci_calculate_mclk_params()
2936 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; in ci_calculate_mclk_params()
2937 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; in ci_calculate_mclk_params()
2938 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; in ci_calculate_mclk_params()
2939 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; in ci_calculate_mclk_params()
2966 if (pi->caps_mclk_ss_support) { in ci_calculate_mclk_params()
3020 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_single_memory_level() local
3050 if (pi->vddc_phase_shed_control) in ci_populate_single_memory_level()
3061 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; in ci_populate_single_memory_level()
3071 if (pi->mclk_stutter_mode_threshold && in ci_populate_single_memory_level()
3072 (memory_clock <= pi->mclk_stutter_mode_threshold) && in ci_populate_single_memory_level()
3073 (!pi->uvd_enabled) && in ci_populate_single_memory_level()
3078 if (pi->mclk_strobe_mode_threshold && in ci_populate_single_memory_level()
3079 (memory_clock <= pi->mclk_strobe_mode_threshold)) in ci_populate_single_memory_level()
3085 if (pi->mclk_edc_enable_threshold && in ci_populate_single_memory_level()
3086 (memory_clock > pi->mclk_edc_enable_threshold)) in ci_populate_single_memory_level()
3089 if (pi->mclk_edc_wr_enable_threshold && in ci_populate_single_memory_level()
3090 (memory_clock > pi->mclk_edc_wr_enable_threshold)) in ci_populate_single_memory_level()
3100 dll_state_on = pi->dll_default_on; in ci_populate_single_memory_level()
3134 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_acpi_level() local
3137 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; in ci_populate_smc_acpi_level()
3138 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; in ci_populate_smc_acpi_level()
3139 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_populate_smc_acpi_level()
3140 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_populate_smc_acpi_level()
3145 if (pi->acpi_vddc) in ci_populate_smc_acpi_level()
3146 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3148 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3150 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
3172 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_populate_smc_acpi_level()
3173 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_populate_smc_acpi_level()
3174 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_populate_smc_acpi_level()
3175 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_populate_smc_acpi_level()
3194 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_smc_acpi_level()
3195 if (pi->acpi_vddci) in ci_populate_smc_acpi_level()
3197 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3200 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3219 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); in ci_populate_smc_acpi_level()
3221 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); in ci_populate_smc_acpi_level()
3223 cpu_to_be32(pi->clock_registers.mpll_func_cntl); in ci_populate_smc_acpi_level()
3225 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); in ci_populate_smc_acpi_level()
3227 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); in ci_populate_smc_acpi_level()
3228 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); in ci_populate_smc_acpi_level()
3229 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); in ci_populate_smc_acpi_level()
3237 cpu_to_be16((u16)pi->mclk_activity_target); in ci_populate_smc_acpi_level()
3251 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_ulv() local
3252 struct ci_ulv_parm *ulv = &pi->ulv; in ci_enable_ulv()
3269 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_ulv_level() local
3276 pi->ulv.supported = false; in ci_populate_ulv_level()
3280 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_populate_ulv_level()
3294 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_ulv_level()
3307 struct ci_power_info *pi = ci_get_pi(adev); in ci_calculate_sclk_params() local
3309 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_calculate_sclk_params()
3310 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_calculate_sclk_params()
3311 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_calculate_sclk_params()
3312 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_calculate_sclk_params()
3331 if (pi->caps_sclk_ss_support) { in ci_calculate_sclk_params()
3364 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_single_graphic_level() local
3382 if (pi->vddc_phase_shed_control) in ci_populate_single_graphic_level()
3398 if (pi->caps_sclk_ds) in ci_populate_single_graphic_level()
3421 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_all_graphic_levels() local
3422 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_graphic_levels()
3423 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_graphic_levels()
3427 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3435 (u16)pi->activity_target[i], in ci_populate_all_graphic_levels()
3436 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3440 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3442 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3445 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
3447 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3448 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()
3453 pi->sram_end); in ci_populate_all_graphic_levels()
3468 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_all_memory_levels() local
3469 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_memory_levels()
3470 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_memory_levels()
3474 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
3484 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3491 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3492 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3493 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()
3494 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3497 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3499 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3500 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()
3503 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3508 pi->sram_end); in ci_populate_all_memory_levels()
3536 struct ci_power_info *pi = ci_get_pi(adev); in ci_setup_default_pcie_tables() local
3538 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) in ci_setup_default_pcie_tables()
3541 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3542 pi->pcie_gen_powersaving = pi->pcie_gen_performance; in ci_setup_default_pcie_tables()
3543 pi->pcie_lane_powersaving = pi->pcie_lane_performance; in ci_setup_default_pcie_tables()
3544 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3545 pi->pcie_gen_performance = pi->pcie_gen_powersaving; in ci_setup_default_pcie_tables()
3546 pi->pcie_lane_performance = pi->pcie_lane_powersaving; in ci_setup_default_pcie_tables()
3550 &pi->dpm_table.pcie_speed_table, in ci_setup_default_pcie_tables()
3554 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3555 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3556 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3558 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3559 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3560 pi->pcie_lane_powersaving.min); in ci_setup_default_pcie_tables()
3561 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, in ci_setup_default_pcie_tables()
3562 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3563 pi->pcie_lane_performance.min); in ci_setup_default_pcie_tables()
3564 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, in ci_setup_default_pcie_tables()
3565 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3566 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3567 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, in ci_setup_default_pcie_tables()
3568 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3569 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3570 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, in ci_setup_default_pcie_tables()
3571 pi->pcie_gen_powersaving.max, in ci_setup_default_pcie_tables()
3572 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3573 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, in ci_setup_default_pcie_tables()
3574 pi->pcie_gen_performance.max, in ci_setup_default_pcie_tables()
3575 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3577 pi->dpm_table.pcie_speed_table.count = 6; in ci_setup_default_pcie_tables()
3584 struct ci_power_info *pi = ci_get_pi(adev); in ci_setup_default_dpm_tables() local
3602 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); in ci_setup_default_dpm_tables()
3605 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3608 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
3611 &pi->dpm_table.vddc_table, in ci_setup_default_dpm_tables()
3614 &pi->dpm_table.vddci_table, in ci_setup_default_dpm_tables()
3617 &pi->dpm_table.mvdd_table, in ci_setup_default_dpm_tables()
3620 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3623 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
3625 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = in ci_setup_default_dpm_tables()
3627 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = in ci_setup_default_dpm_tables()
3629 pi->dpm_table.sclk_table.count++; in ci_setup_default_dpm_tables()
3633 pi->dpm_table.mclk_table.count = 0; in ci_setup_default_dpm_tables()
3636 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != in ci_setup_default_dpm_tables()
3638 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = in ci_setup_default_dpm_tables()
3640 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = in ci_setup_default_dpm_tables()
3642 pi->dpm_table.mclk_table.count++; in ci_setup_default_dpm_tables()
3647 pi->dpm_table.vddc_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3649 pi->dpm_table.vddc_table.dpm_levels[i].param1 = in ci_setup_default_dpm_tables()
3651 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3653 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()
3658 pi->dpm_table.vddci_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3660 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3662 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3668 pi->dpm_table.mvdd_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3670 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3672 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3678 memcpy(&(pi->golden_dpm_table), &(pi->dpm_table), in ci_setup_default_dpm_tables()
3702 struct ci_power_info *pi = ci_get_pi(adev); in ci_init_smc_table() local
3703 struct ci_ulv_parm *ulv = &pi->ulv; in ci_init_smc_table()
3705 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table()
3712 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) in ci_init_smc_table()
3727 ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv); in ci_init_smc_table()
3774 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, in ci_init_smc_table()
3775 pi->vbios_boot_state.sclk_bootup_value, in ci_init_smc_table()
3776 (u32 *)&pi->smc_state_table.GraphicsBootLevel); in ci_init_smc_table()
3778 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, in ci_init_smc_table()
3779 pi->vbios_boot_state.mclk_bootup_value, in ci_init_smc_table()
3780 (u32 *)&pi->smc_state_table.MemoryBootLevel); in ci_init_smc_table()
3782 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; in ci_init_smc_table()
3783 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; in ci_init_smc_table()
3784 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; in ci_init_smc_table()
3801 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * in ci_init_smc_table()
3803 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * in ci_init_smc_table()
3811 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3813 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) in ci_init_smc_table()
3837 pi->dpm_table_start + in ci_init_smc_table()
3841 pi->sram_end); in ci_init_smc_table()
3867 struct ci_power_info *pi = ci_get_pi(adev); in ci_trim_pcie_dpm_states() local
3868 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; in ci_trim_pcie_dpm_states()
3898 struct ci_power_info *pi = ci_get_pi(adev); in ci_trim_dpm_states() local
3910 &pi->dpm_table.sclk_table, in ci_trim_dpm_states()
3915 &pi->dpm_table.mclk_table, in ci_trim_dpm_states()
3962 struct ci_power_info *pi = ci_get_pi(adev); in ci_upload_dpm_level_enable_mask() local
3967 if (!pi->sclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3968 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3971 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3977 if (!pi->mclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3978 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3981 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3988 if (!pi->pcie_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3989 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3992 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
4005 struct ci_power_info *pi = ci_get_pi(adev); in ci_find_dpm_states_clocks_in_dpm_table() local
4007 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
4009 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
4013 pi->need_update_smu7_dpm_table = 0; in ci_find_dpm_states_clocks_in_dpm_table()
4021 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
4025 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
4034 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
4038 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
4044 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_and_upload_sclk_mclk_dpm_levels() local
4048 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_and_upload_sclk_mclk_dpm_levels()
4051 if (!pi->need_update_smu7_dpm_table) in ci_populate_and_upload_sclk_mclk_dpm_levels()
4054 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
4057 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
4060 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
4066 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
4077 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_uvd_dpm() local
4087 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()
4091 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; in ci_enable_uvd_dpm()
4093 if (!pi->caps_uvd_dpm) in ci_enable_uvd_dpm()
4100 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); in ci_enable_uvd_dpm()
4102 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
4103 pi->uvd_enabled = true; in ci_enable_uvd_dpm()
4104 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_enable_uvd_dpm()
4107 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
4110 if (pi->uvd_enabled) { in ci_enable_uvd_dpm()
4111 pi->uvd_enabled = false; in ci_enable_uvd_dpm()
4112 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; in ci_enable_uvd_dpm()
4115 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
4126 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_vce_dpm() local
4136 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; in ci_enable_vce_dpm()
4139 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; in ci_enable_vce_dpm()
4141 if (!pi->caps_vce_dpm) in ci_enable_vce_dpm()
4148 pi->dpm_level_enable_mask.vce_dpm_enable_mask); in ci_enable_vce_dpm()
4159 struct ci_power_info *pi = ci_get_pi(adev);
4169 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4172 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4174 if (!pi->caps_samu_dpm)
4181 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4190 struct ci_power_info *pi = ci_get_pi(adev);
4200 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4203 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4205 if (!pi->caps_acp_dpm)
4212 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4223 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_uvd_dpm() local
4229 if (pi->caps_uvd_dpm || in ci_update_uvd_dpm()
4231 pi->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_dpm()
4233 pi->smc_state_table.UvdBootLevel = in ci_update_uvd_dpm()
4238 tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT); in ci_update_uvd_dpm()
4269 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_vce_dpm() local
4275 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev); in ci_update_vce_dpm()
4278 tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT); in ci_update_vce_dpm()
4299 struct ci_power_info *pi = ci_get_pi(adev);
4303 pi->smc_state_table.AcpBootLevel = 0;
4307 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4318 struct ci_power_info *pi = ci_get_pi(adev); in ci_generate_dpm_level_enable_mask() local
4325 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4326 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); in ci_generate_dpm_level_enable_mask()
4327 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4328 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); in ci_generate_dpm_level_enable_mask()
4329 pi->last_mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4330 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_generate_dpm_level_enable_mask()
4331 if (pi->uvd_enabled) { in ci_generate_dpm_level_enable_mask()
4332 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) in ci_generate_dpm_level_enable_mask()
4333 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_generate_dpm_level_enable_mask()
4335 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4336 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); in ci_generate_dpm_level_enable_mask()
4357 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_force_performance_level() local
4362 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4363 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4365 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; in ci_dpm_force_performance_level()
4382 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4383 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4385 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4402 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4403 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4405 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4423 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4424 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4426 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4439 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4440 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4442 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4455 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4456 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4458 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_dpm_force_performance_level()
4472 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_performance_level()
4775 struct ci_power_info *pi = ci_get_pi(adev); in ci_initialize_mc_reg_table() local
4777 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; in ci_initialize_mc_reg_table()
4835 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_mc_reg_addresses() local
4838 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { in ci_populate_mc_reg_addresses()
4839 if (pi->mc_reg_table.valid_flag & (1 << j)) { in ci_populate_mc_reg_addresses()
4842 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); in ci_populate_mc_reg_addresses()
4843 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); in ci_populate_mc_reg_addresses()
4871 struct ci_power_info *pi = ci_get_pi(adev); in ci_convert_mc_reg_table_entry_to_smc() local
4874 for(i = 0; i < pi->mc_reg_table.num_entries; i++) { in ci_convert_mc_reg_table_entry_to_smc()
4875 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in ci_convert_mc_reg_table_entry_to_smc()
4879 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) in ci_convert_mc_reg_table_entry_to_smc()
4882 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], in ci_convert_mc_reg_table_entry_to_smc()
4883 mc_reg_table_data, pi->mc_reg_table.last, in ci_convert_mc_reg_table_entry_to_smc()
4884 pi->mc_reg_table.valid_flag); in ci_convert_mc_reg_table_entry_to_smc()
4890 struct ci_power_info *pi = ci_get_pi(adev); in ci_convert_mc_reg_table_to_smc() local
4893 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) in ci_convert_mc_reg_table_to_smc()
4895 pi->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
4901 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_initial_mc_reg_table() local
4904 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_populate_initial_mc_reg_table()
4906 ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4909 ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4912 pi->mc_reg_table_start, in ci_populate_initial_mc_reg_table()
4913 (u8 *)&pi->smc_mc_reg_table, in ci_populate_initial_mc_reg_table()
4915 pi->sram_end); in ci_populate_initial_mc_reg_table()
4920 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_and_upload_mc_reg_table() local
4922 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
4925 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_update_and_upload_mc_reg_table()
4927 ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table); in ci_update_and_upload_mc_reg_table()
4930 pi->mc_reg_table_start + in ci_update_and_upload_mc_reg_table()
4932 (u8 *)&pi->smc_mc_reg_table.data[0], in ci_update_and_upload_mc_reg_table()
4934 pi->dpm_table.mclk_table.count, in ci_update_and_upload_mc_reg_table()
4935 pi->sram_end); in ci_update_and_upload_mc_reg_table()
5001 struct ci_power_info *pi = ci_get_pi(adev); in ci_request_link_speed_change_before_state_change() local
5006 if (pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID) in ci_request_link_speed_change_before_state_change()
5009 current_link_speed = pi->force_pcie_gen; in ci_request_link_speed_change_before_state_change()
5011 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; in ci_request_link_speed_change_before_state_change()
5012 pi->pspp_notify_required = false; in ci_request_link_speed_change_before_state_change()
5019 pi->force_pcie_gen = AMDGPU_PCIE_GEN2; in ci_request_link_speed_change_before_state_change()
5027 pi->force_pcie_gen = ci_get_current_pcie_speed(adev); in ci_request_link_speed_change_before_state_change()
5032 pi->pspp_notify_required = true; in ci_request_link_speed_change_before_state_change()
5040 struct ci_power_info *pi = ci_get_pi(adev); in ci_notify_link_speed_change_after_state_change() local
5045 if (pi->pspp_notify_required) { in ci_notify_link_speed_change_after_state_change()
5065 struct ci_power_info *pi = ci_get_pi(adev); in ci_set_private_data_variables_based_on_pptable() local
5086 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
5087 pi->max_vddc_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
5090 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
5091 pi->max_vddci_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
5108 struct ci_power_info *pi = ci_get_pi(adev); in ci_patch_with_vddc_leakage() local
5109 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; in ci_patch_with_vddc_leakage()
5122 struct ci_power_info *pi = ci_get_pi(adev); in ci_patch_with_vddci_leakage() local
5123 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; in ci_patch_with_vddci_leakage()
5243 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_current_ps() local
5245 pi->current_rps = *rps; in ci_update_current_ps()
5246 pi->current_ps = *new_ps; in ci_update_current_ps()
5247 pi->current_rps.ps_priv = &pi->current_ps; in ci_update_current_ps()
5248 adev->pm.dpm.current_ps = &pi->current_rps; in ci_update_current_ps()
5255 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_requested_ps() local
5257 pi->requested_rps = *rps; in ci_update_requested_ps()
5258 pi->requested_ps = *new_ps; in ci_update_requested_ps()
5259 pi->requested_rps.ps_priv = &pi->requested_ps; in ci_update_requested_ps()
5260 adev->pm.dpm.requested_ps = &pi->requested_rps; in ci_update_requested_ps()
5266 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_pre_set_power_state() local
5272 ci_apply_state_adjust_rules(adev, &pi->requested_rps); in ci_dpm_pre_set_power_state()
5280 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_post_set_power_state() local
5281 struct amdgpu_ps *new_ps = &pi->requested_rps; in ci_dpm_post_set_power_state()
5296 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_enable() local
5300 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_dpm_enable()
5308 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5311 pi->caps_dynamic_ac_timing = false; in ci_dpm_enable()
5313 if (pi->dynamic_ss) in ci_dpm_enable()
5315 if (pi->thermal_protection) in ci_dpm_enable()
5345 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5419 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_disable() local
5434 if (pi->thermal_protection) in ci_dpm_disable()
5456 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_set_power_state() local
5457 struct amdgpu_ps *new_ps = &pi->requested_rps; in ci_dpm_set_power_state()
5458 struct amdgpu_ps *old_ps = &pi->current_rps; in ci_dpm_set_power_state()
5462 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5491 if (pi->caps_dynamic_ac_timing) { in ci_dpm_set_power_state()
5513 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5583 struct ci_power_info *pi = ci_get_pi(adev); in ci_parse_pplib_clock_info() local
5595 pi->sys_pcie_mask, in ci_parse_pplib_clock_info()
5596 pi->vbios_boot_state.pcie_gen_bootup_value, in ci_parse_pplib_clock_info()
5599 pi->vbios_boot_state.pcie_lane_bootup_value, in ci_parse_pplib_clock_info()
5603 pi->acpi_pcie_gen = pl->pcie_gen; in ci_parse_pplib_clock_info()
5607 pi->ulv.supported = true; in ci_parse_pplib_clock_info()
5608 pi->ulv.pl = *pl; in ci_parse_pplib_clock_info()
5609 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; in ci_parse_pplib_clock_info()
5614 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; in ci_parse_pplib_clock_info()
5615 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; in ci_parse_pplib_clock_info()
5616 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; in ci_parse_pplib_clock_info()
5617 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; in ci_parse_pplib_clock_info()
5622 pi->use_pcie_powersaving_levels = true; in ci_parse_pplib_clock_info()
5623 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5624 pi->pcie_gen_powersaving.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5625 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5626 pi->pcie_gen_powersaving.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5627 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5628 pi->pcie_lane_powersaving.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5629 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5630 pi->pcie_lane_powersaving.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5633 pi->use_pcie_performance_levels = true; in ci_parse_pplib_clock_info()
5634 if (pi->pcie_gen_performance.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5635 pi->pcie_gen_performance.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5636 if (pi->pcie_gen_performance.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5637 pi->pcie_gen_performance.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5638 if (pi->pcie_lane_performance.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5639 pi->pcie_lane_performance.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5640 if (pi->pcie_lane_performance.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5641 pi->pcie_lane_performance.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5840 struct ci_power_info *pi; in ci_dpm_init() local
5843 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); in ci_dpm_init()
5844 if (pi == NULL) in ci_dpm_init()
5846 adev->pm.dpm.priv = pi; in ci_dpm_init()
5848 pi->sys_pcie_mask = in ci_dpm_init()
5851 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; in ci_dpm_init()
5853 pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1; in ci_dpm_init()
5854 pi->pcie_gen_performance.min = AMDGPU_PCIE_GEN3; in ci_dpm_init()
5855 pi->pcie_gen_powersaving.max = AMDGPU_PCIE_GEN1; in ci_dpm_init()
5856 pi->pcie_gen_powersaving.min = AMDGPU_PCIE_GEN3; in ci_dpm_init()
5858 pi->pcie_lane_performance.max = 0; in ci_dpm_init()
5859 pi->pcie_lane_performance.min = 16; in ci_dpm_init()
5860 pi->pcie_lane_powersaving.max = 0; in ci_dpm_init()
5861 pi->pcie_lane_powersaving.min = 16; in ci_dpm_init()
5863 ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state); in ci_dpm_init()
5887 pi->dll_default_on = false; in ci_dpm_init()
5888 pi->sram_end = SMC_RAM_END; in ci_dpm_init()
5890 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5891 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5892 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5893 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5894 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5895 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5896 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5897 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5899 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; in ci_dpm_init()
5901 pi->sclk_dpm_key_disabled = 0; in ci_dpm_init()
5902 pi->mclk_dpm_key_disabled = 0; in ci_dpm_init()
5903 pi->pcie_dpm_key_disabled = 0; in ci_dpm_init()
5904 pi->thermal_sclk_dpm_enabled = 0; in ci_dpm_init()
5907 pi->caps_sclk_ds = true; in ci_dpm_init()
5909 pi->caps_sclk_ds = false; in ci_dpm_init()
5911 pi->mclk_strobe_mode_threshold = 40000; in ci_dpm_init()
5912 pi->mclk_stutter_mode_threshold = 40000; in ci_dpm_init()
5913 pi->mclk_edc_enable_threshold = 40000; in ci_dpm_init()
5914 pi->mclk_edc_wr_enable_threshold = 40000; in ci_dpm_init()
5918 pi->caps_fps = false; in ci_dpm_init()
5920 pi->caps_sclk_throttle_low_notification = false; in ci_dpm_init()
5922 pi->caps_uvd_dpm = true; in ci_dpm_init()
5923 pi->caps_vce_dpm = true; in ci_dpm_init()
5957 pi->thermal_temp_setting.temperature_low = 94500; in ci_dpm_init()
5958 pi->thermal_temp_setting.temperature_high = 95000; in ci_dpm_init()
5959 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5961 pi->thermal_temp_setting.temperature_low = 99500; in ci_dpm_init()
5962 pi->thermal_temp_setting.temperature_high = 100000; in ci_dpm_init()
5963 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5966 pi->uvd_enabled = false; in ci_dpm_init()
5968 dpm_table = &pi->smc_state_table; in ci_dpm_init()
6017 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
6018 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
6019 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
6021 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
6023 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
6027 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
6029 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
6036 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
6038 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
6043 pi->vddc_phase_shed_control = true; in ci_dpm_init()
6046 pi->pcie_performance_request = in ci_dpm_init()
6049 pi->pcie_performance_request = false; in ci_dpm_init()
6054 pi->caps_sclk_ss_support = true; in ci_dpm_init()
6055 pi->caps_mclk_ss_support = true; in ci_dpm_init()
6056 pi->dynamic_ss = true; in ci_dpm_init()
6058 pi->caps_sclk_ss_support = false; in ci_dpm_init()
6059 pi->caps_mclk_ss_support = false; in ci_dpm_init()
6060 pi->dynamic_ss = true; in ci_dpm_init()
6064 pi->thermal_protection = true; in ci_dpm_init()
6066 pi->thermal_protection = false; in ci_dpm_init()
6068 pi->caps_dynamic_ac_timing = true; in ci_dpm_init()
6070 pi->uvd_power_gated = true; in ci_dpm_init()
6078 pi->fan_ctrl_is_in_default_mode = true; in ci_dpm_init()
6088 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_debugfs_print_current_performance_level() local
6089 struct amdgpu_ps *rps = &pi->current_rps; in ci_dpm_debugfs_print_current_performance_level()
6104 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); in ci_dpm_debugfs_print_current_performance_level()
6186 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_get_sclk() local
6187 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_sclk()
6198 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_get_mclk() local
6199 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_mclk()
6542 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_print_clock_levels() local
6543 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; in ci_dpm_print_clock_levels()
6544 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; in ci_dpm_print_clock_levels()
6545 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; in ci_dpm_print_clock_levels()
6610 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_force_clock_level() local
6620 if (!pi->sclk_dpm_key_disabled) in ci_dpm_force_clock_level()
6623 pi->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); in ci_dpm_force_clock_level()
6627 if (!pi->mclk_dpm_key_disabled) in ci_dpm_force_clock_level()
6630 pi->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); in ci_dpm_force_clock_level()
6635 uint32_t tmp = mask & pi->dpm_level_enable_mask.pcie_dpm_enable_mask; in ci_dpm_force_clock_level()
6637 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_clock_level()
6657 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_get_sclk_od() local
6658 struct ci_single_dpm_table *sclk_table = &(pi->dpm_table.sclk_table); in ci_dpm_get_sclk_od()
6660 &(pi->golden_dpm_table.sclk_table); in ci_dpm_get_sclk_od()
6674 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_set_sclk_od() local
6677 &(pi->golden_dpm_table.sclk_table); in ci_dpm_set_sclk_od()
6693 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_get_mclk_od() local
6694 struct ci_single_dpm_table *mclk_table = &(pi->dpm_table.mclk_table); in ci_dpm_get_mclk_od()
6696 &(pi->golden_dpm_table.mclk_table); in ci_dpm_get_mclk_od()
6710 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_set_mclk_od() local
6713 &(pi->golden_dpm_table.mclk_table); in ci_dpm_set_mclk_od()