3362 					    SMU7_Discrete_GraphicsLevel *graphic_level)  in ci_populate_single_graphic_level()  argument
3367 	ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level);  in ci_populate_single_graphic_level()
3373 					    engine_clock, &graphic_level->MinVddc);  in ci_populate_single_graphic_level()
3377 	graphic_level->SclkFrequency = engine_clock;  in ci_populate_single_graphic_level()
3379 	graphic_level->Flags =  0;  in ci_populate_single_graphic_level()
3380 	graphic_level->MinVddcPhases = 1;  in ci_populate_single_graphic_level()
3386 						      &graphic_level->MinVddcPhases);  in ci_populate_single_graphic_level()
3388 	graphic_level->ActivityLevel = sclk_activity_level_t;  in ci_populate_single_graphic_level()
3390 	graphic_level->CcPwrDynRm = 0;  in ci_populate_single_graphic_level()
3391 	graphic_level->CcPwrDynRm1 = 0;  in ci_populate_single_graphic_level()
3392 	graphic_level->EnabledForThrottle = 1;  in ci_populate_single_graphic_level()
3393 	graphic_level->UpH = 0;  in ci_populate_single_graphic_level()
3394 	graphic_level->DownH = 0;  in ci_populate_single_graphic_level()
3395 	graphic_level->VoltageDownH = 0;  in ci_populate_single_graphic_level()
3396 	graphic_level->PowerThrottle = 0;  in ci_populate_single_graphic_level()
3399 		graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(engine_clock,  in ci_populate_single_graphic_level()
3402 	graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;  in ci_populate_single_graphic_level()
3404 	graphic_level->Flags = cpu_to_be32(graphic_level->Flags);  in ci_populate_single_graphic_level()
3405 	graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);  in ci_populate_single_graphic_level()
3406 	graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);  in ci_populate_single_graphic_level()
3407 	graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);  in ci_populate_single_graphic_level()
3408 	graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);  in ci_populate_single_graphic_level()
3409 	graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);  in ci_populate_single_graphic_level()
3410 	graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);  in ci_populate_single_graphic_level()
3411 	graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);  in ci_populate_single_graphic_level()
3412 	graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);  in ci_populate_single_graphic_level()
3413 	graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);  in ci_populate_single_graphic_level()
3414 	graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);  in ci_populate_single_graphic_level()