2633 					const u32 engine_clock,  in ci_register_patching_mc_arb()  argument
2647 			tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;  in ci_register_patching_mc_arb()
2651 			tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;  in ci_register_patching_mc_arb()
3304 				    u32 engine_clock,  in ci_calculate_sclk_params()  argument
3320 						 engine_clock, false, &dividers);  in ci_calculate_sclk_params()
3333 		u32 vco_freq = engine_clock * dividers.post_div;  in ci_calculate_sclk_params()
3349 	sclk->SclkFrequency = engine_clock;  in ci_calculate_sclk_params()
3360 					    u32 engine_clock,  in ci_populate_single_graphic_level()  argument
3367 	ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level);  in ci_populate_single_graphic_level()
3373 					    engine_clock, &graphic_level->MinVddc);  in ci_populate_single_graphic_level()
3377 	graphic_level->SclkFrequency = engine_clock;  in ci_populate_single_graphic_level()
3385 						      engine_clock,  in ci_populate_single_graphic_level()
3399 		graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(engine_clock,  in ci_populate_single_graphic_level()