Lines Matching refs:dpm_levels
2694 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2695 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2753 if (dpm_table->dpm_levels[i-1].enabled) in ci_get_dpm_level_enable_mask_value()
2771 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level()
2773 amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level()
3434 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
3480 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()
3483 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
3523 dpm_table->dpm_levels[i].enabled = false; in ci_reset_single_dpm_table()
3529 dpm_table->dpm_levels[index].value = pcie_gen; in ci_setup_pcie_table_entry()
3530 dpm_table->dpm_levels[index].param1 = pcie_lanes; in ci_setup_pcie_table_entry()
3531 dpm_table->dpm_levels[index].enabled = true; in ci_setup_pcie_table_entry()
3623 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
3625 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = in ci_setup_default_dpm_tables()
3627 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = in ci_setup_default_dpm_tables()
3636 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != in ci_setup_default_dpm_tables()
3638 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = in ci_setup_default_dpm_tables()
3640 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = in ci_setup_default_dpm_tables()
3647 pi->dpm_table.vddc_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3649 pi->dpm_table.vddc_table.dpm_levels[i].param1 = in ci_setup_default_dpm_tables()
3651 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3658 pi->dpm_table.vddci_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3660 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3668 pi->dpm_table.mvdd_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3670 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3691 if (value == table->dpm_levels[i].value) { in ci_find_boot_level()
3855 if ((dpm_table->dpm_levels[i].value < low_limit) || in ci_trim_single_dpm_states()
3856 (dpm_table->dpm_levels[i].value > high_limit)) in ci_trim_single_dpm_states()
3857 dpm_table->dpm_levels[i].enabled = false; in ci_trim_single_dpm_states()
3859 dpm_table->dpm_levels[i].enabled = true; in ci_trim_single_dpm_states()
3872 if ((pcie_table->dpm_levels[i].value < speed_low) || in ci_trim_pcie_dpm_states()
3873 (pcie_table->dpm_levels[i].param1 < lanes_low) || in ci_trim_pcie_dpm_states()
3874 (pcie_table->dpm_levels[i].value > speed_high) || in ci_trim_pcie_dpm_states()
3875 (pcie_table->dpm_levels[i].param1 > lanes_high)) in ci_trim_pcie_dpm_states()
3876 pcie_table->dpm_levels[i].enabled = false; in ci_trim_pcie_dpm_states()
3878 pcie_table->dpm_levels[i].enabled = true; in ci_trim_pcie_dpm_states()
3882 if (pcie_table->dpm_levels[i].enabled) { in ci_trim_pcie_dpm_states()
3884 if (pcie_table->dpm_levels[j].enabled) { in ci_trim_pcie_dpm_states()
3885 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) && in ci_trim_pcie_dpm_states()
3886 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1)) in ci_trim_pcie_dpm_states()
3887 pcie_table->dpm_levels[j].enabled = false; in ci_trim_pcie_dpm_states()
4016 if (sclk == sclk_table->dpm_levels[i].value) in ci_find_dpm_states_clocks_in_dpm_table()
4029 if (mclk == mclk_table->dpm_levels[i].value) in ci_find_dpm_states_clocks_in_dpm_table()
4055 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
4058 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
4895 pi->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
6556 if (clock > sclk_table->dpm_levels[i].value) in ci_dpm_print_clock_levels()
6564 i, sclk_table->dpm_levels[i].value / 100, in ci_dpm_print_clock_levels()
6572 if (clock > mclk_table->dpm_levels[i].value) in ci_dpm_print_clock_levels()
6580 i, mclk_table->dpm_levels[i].value / 100, in ci_dpm_print_clock_levels()
6586 if (pcie_speed != pcie_table->dpm_levels[i].value) in ci_dpm_print_clock_levels()
6594 (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x1" : in ci_dpm_print_clock_levels()
6595 (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" : in ci_dpm_print_clock_levels()
6596 (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "", in ci_dpm_print_clock_levels()
6663 value = (sclk_table->dpm_levels[sclk_table->count - 1].value - in ci_dpm_get_sclk_od()
6664 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) * in ci_dpm_get_sclk_od()
6666 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; in ci_dpm_get_sclk_od()
6683 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * in ci_dpm_set_sclk_od()
6685 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; in ci_dpm_set_sclk_od()
6699 value = (mclk_table->dpm_levels[mclk_table->count - 1].value - in ci_dpm_get_mclk_od()
6700 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) * in ci_dpm_get_mclk_od()
6702 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; in ci_dpm_get_mclk_od()
6719 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * in ci_dpm_set_mclk_od()
6721 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; in ci_dpm_set_mclk_od()