493 amdgpu_atombios_dp_update_vs_emph(struct amdgpu_atombios_dp_link_train_info *dp_info)  in amdgpu_atombios_dp_update_vs_emph()  argument
496 	amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder,  in amdgpu_atombios_dp_update_vs_emph()
498 					       0, dp_info->train_set[0]); /* sets all lanes at once */  in amdgpu_atombios_dp_update_vs_emph()
501 	drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,  in amdgpu_atombios_dp_update_vs_emph()
502 			  dp_info->train_set, dp_info->dp_lane_count);  in amdgpu_atombios_dp_update_vs_emph()
506 amdgpu_atombios_dp_set_tp(struct amdgpu_atombios_dp_link_train_info *dp_info, int tp)  in amdgpu_atombios_dp_set_tp()  argument
522 	amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0);  in amdgpu_atombios_dp_set_tp()
525 	drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);  in amdgpu_atombios_dp_set_tp()
529 amdgpu_atombios_dp_link_train_init(struct amdgpu_atombios_dp_link_train_info *dp_info)  in amdgpu_atombios_dp_link_train_init()  argument
531 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder);  in amdgpu_atombios_dp_link_train_init()
536 	amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);  in amdgpu_atombios_dp_link_train_init()
539 	if (dp_info->dpcd[3] & 0x1)  in amdgpu_atombios_dp_link_train_init()
540 		drm_dp_dpcd_writeb(dp_info->aux,  in amdgpu_atombios_dp_link_train_init()
543 		drm_dp_dpcd_writeb(dp_info->aux,  in amdgpu_atombios_dp_link_train_init()
547 		drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);  in amdgpu_atombios_dp_link_train_init()
550 	tmp = dp_info->dp_lane_count;  in amdgpu_atombios_dp_link_train_init()
551 	if (drm_dp_enhanced_frame_cap(dp_info->dpcd))  in amdgpu_atombios_dp_link_train_init()
553 	drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);  in amdgpu_atombios_dp_link_train_init()
556 	tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);  in amdgpu_atombios_dp_link_train_init()
557 	drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);  in amdgpu_atombios_dp_link_train_init()
560 	amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,  in amdgpu_atombios_dp_link_train_init()
564 	drm_dp_dpcd_writeb(dp_info->aux,  in amdgpu_atombios_dp_link_train_init()
572 amdgpu_atombios_dp_link_train_finish(struct amdgpu_atombios_dp_link_train_info *dp_info)  in amdgpu_atombios_dp_link_train_finish()  argument
577 	drm_dp_dpcd_writeb(dp_info->aux,  in amdgpu_atombios_dp_link_train_finish()
582 	amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,  in amdgpu_atombios_dp_link_train_finish()
589 amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_info)  in amdgpu_atombios_dp_link_train_cr()  argument
595 	amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);  in amdgpu_atombios_dp_link_train_cr()
596 	memset(dp_info->train_set, 0, 4);  in amdgpu_atombios_dp_link_train_cr()
597 	amdgpu_atombios_dp_update_vs_emph(dp_info);  in amdgpu_atombios_dp_link_train_cr()
603 	dp_info->tries = 0;  in amdgpu_atombios_dp_link_train_cr()
606 		drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);  in amdgpu_atombios_dp_link_train_cr()
608 		if (drm_dp_dpcd_read_link_status(dp_info->aux,  in amdgpu_atombios_dp_link_train_cr()
609 						 dp_info->link_status) <= 0) {  in amdgpu_atombios_dp_link_train_cr()
614 		if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {  in amdgpu_atombios_dp_link_train_cr()
619 		for (i = 0; i < dp_info->dp_lane_count; i++) {  in amdgpu_atombios_dp_link_train_cr()
620 			if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)  in amdgpu_atombios_dp_link_train_cr()
623 		if (i == dp_info->dp_lane_count) {  in amdgpu_atombios_dp_link_train_cr()
628 		if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {  in amdgpu_atombios_dp_link_train_cr()
629 			++dp_info->tries;  in amdgpu_atombios_dp_link_train_cr()
630 			if (dp_info->tries == 5) {  in amdgpu_atombios_dp_link_train_cr()
635 			dp_info->tries = 0;  in amdgpu_atombios_dp_link_train_cr()
637 		voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;  in amdgpu_atombios_dp_link_train_cr()
640 		amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,  in amdgpu_atombios_dp_link_train_cr()
641 					     dp_info->train_set);  in amdgpu_atombios_dp_link_train_cr()
643 		amdgpu_atombios_dp_update_vs_emph(dp_info);  in amdgpu_atombios_dp_link_train_cr()
650 			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,  in amdgpu_atombios_dp_link_train_cr()
651 			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>  in amdgpu_atombios_dp_link_train_cr()
658 amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_info)  in amdgpu_atombios_dp_link_train_ce()  argument
662 	if (dp_info->tp3_supported)  in amdgpu_atombios_dp_link_train_ce()
663 		amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);  in amdgpu_atombios_dp_link_train_ce()
665 		amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);  in amdgpu_atombios_dp_link_train_ce()
668 	dp_info->tries = 0;  in amdgpu_atombios_dp_link_train_ce()
671 		drm_dp_link_train_channel_eq_delay(dp_info->dpcd);  in amdgpu_atombios_dp_link_train_ce()
673 		if (drm_dp_dpcd_read_link_status(dp_info->aux,  in amdgpu_atombios_dp_link_train_ce()
674 						 dp_info->link_status) <= 0) {  in amdgpu_atombios_dp_link_train_ce()
679 		if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {  in amdgpu_atombios_dp_link_train_ce()
685 		if (dp_info->tries > 5) {  in amdgpu_atombios_dp_link_train_ce()
691 		amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,  in amdgpu_atombios_dp_link_train_ce()
692 					     dp_info->train_set);  in amdgpu_atombios_dp_link_train_ce()
694 		amdgpu_atombios_dp_update_vs_emph(dp_info);  in amdgpu_atombios_dp_link_train_ce()
695 		dp_info->tries++;  in amdgpu_atombios_dp_link_train_ce()
703 			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,  in amdgpu_atombios_dp_link_train_ce()
704 			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)  in amdgpu_atombios_dp_link_train_ce()
719 	struct amdgpu_atombios_dp_link_train_info dp_info;  in amdgpu_atombios_dp_link_train()  local
738 			dp_info.tp3_supported = true;  in amdgpu_atombios_dp_link_train()
740 			dp_info.tp3_supported = false;  in amdgpu_atombios_dp_link_train()
742 		dp_info.tp3_supported = false;  in amdgpu_atombios_dp_link_train()
745 	memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);  in amdgpu_atombios_dp_link_train()
746 	dp_info.adev = adev;  in amdgpu_atombios_dp_link_train()
747 	dp_info.encoder = encoder;  in amdgpu_atombios_dp_link_train()
748 	dp_info.connector = connector;  in amdgpu_atombios_dp_link_train()
749 	dp_info.dp_lane_count = dig_connector->dp_lane_count;  in amdgpu_atombios_dp_link_train()
750 	dp_info.dp_clock = dig_connector->dp_clock;  in amdgpu_atombios_dp_link_train()
751 	dp_info.aux = &amdgpu_connector->ddc_bus->aux;  in amdgpu_atombios_dp_link_train()
753 	if (amdgpu_atombios_dp_link_train_init(&dp_info))  in amdgpu_atombios_dp_link_train()
755 	if (amdgpu_atombios_dp_link_train_cr(&dp_info))  in amdgpu_atombios_dp_link_train()
757 	if (amdgpu_atombios_dp_link_train_ce(&dp_info))  in amdgpu_atombios_dp_link_train()
760 	if (amdgpu_atombios_dp_link_train_finish(&dp_info))  in amdgpu_atombios_dp_link_train()