Lines Matching refs:firmware

251 int amdgpu_ucode_validate(const struct firmware *fw)  in amdgpu_ucode_validate()
339 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP || in amdgpu_ucode_init_single_fw()
416 if (!adev->firmware.fw_size) { in amdgpu_ucode_init_bo()
422 err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, in amdgpu_ucode_init_bo()
424 &adev->firmware.fw_buf, in amdgpu_ucode_init_bo()
425 &adev->firmware.fw_buf_mc, in amdgpu_ucode_init_bo()
426 &adev->firmware.fw_buf_ptr); in amdgpu_ucode_init_bo()
433 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); in amdgpu_ucode_init_bo()
439 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { in amdgpu_ucode_init_bo()
441 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3; in amdgpu_ucode_init_bo()
443 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4; in amdgpu_ucode_init_bo()
445 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM; in amdgpu_ucode_init_bo()
448 for (i = 0; i < adev->firmware.max_ucodes; i++) { in amdgpu_ucode_init_bo()
449 ucode = &adev->firmware.ucode[i]; in amdgpu_ucode_init_bo()
452 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset, in amdgpu_ucode_init_bo()
453 adev->firmware.fw_buf_ptr + fw_offset); in amdgpu_ucode_init_bo()
455 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { in amdgpu_ucode_init_bo()
458 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset, in amdgpu_ucode_init_bo()
459 adev->firmware.fw_buf_ptr + fw_offset); in amdgpu_ucode_init_bo()
469 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; in amdgpu_ucode_init_bo()
479 if (!adev->firmware.fw_size) in amdgpu_ucode_fini_bo()
482 for (i = 0; i < adev->firmware.max_ucodes; i++) { in amdgpu_ucode_fini_bo()
483 ucode = &adev->firmware.ucode[i]; in amdgpu_ucode_fini_bo()
490 amdgpu_bo_free_kernel(&adev->firmware.fw_buf, in amdgpu_ucode_fini_bo()
491 &adev->firmware.fw_buf_mc, in amdgpu_ucode_fini_bo()
492 &adev->firmware.fw_buf_ptr); in amdgpu_ucode_fini_bo()