Lines Matching defs:amdgpu_crtc

386 struct amdgpu_crtc {  struct
387 	struct drm_crtc base;
388 	int crtc_id;
389 	bool enabled;
390 	bool can_tile;
391 	uint32_t crtc_offset;
392 	struct drm_gem_object *cursor_bo;
393 	uint64_t cursor_addr;
394 	int cursor_x;
395 	int cursor_y;
396 	int cursor_hot_x;
397 	int cursor_hot_y;
398 	int cursor_width;
399 	int cursor_height;
400 	int max_cursor_width;
401 	int max_cursor_height;
402 	enum amdgpu_rmx_type rmx_type;
403 	u8 h_border;
404 	u8 v_border;
405 	fixed20_12 vsc;
406 	fixed20_12 hsc;
407 	struct drm_display_mode native_mode;
408 	u32 pll_id;
410 	struct amdgpu_flip_work *pflip_works;
411 	enum amdgpu_flip_status pflip_status;
412 	int deferred_flip_completion;
414 	struct amdgpu_atom_ss ss;
415 	bool ss_enabled;
416 	u32 adjusted_clock;
417 	int bpc;
418 	u32 pll_reference_div;
419 	u32 pll_post_div;
420 	u32 pll_flags;
421 	struct drm_encoder *encoder;
422 	struct drm_connector *connector;
424 	u32 line_time;
425 	u32 wm_low;
426 	u32 wm_high;
427 	u32 lb_vblank_lead_lines;
428 	struct drm_display_mode hw_mode;
430 	struct hrtimer vblank_timer;
431 	enum amdgpu_interrupt_state vsync_timer_enabled;
433 	int otg_inst;
434 	struct drm_pending_vblank_event *event;