119 		se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;  in amdgpu_debugfs_process_reg_op()
120 		sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;  in amdgpu_debugfs_process_reg_op()
121 		instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;  in amdgpu_debugfs_process_reg_op()
132 		me = (*pos & GENMASK_ULL(33, 24)) >> 24;  in amdgpu_debugfs_process_reg_op()
133 		pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;  in amdgpu_debugfs_process_reg_op()
134 		queue = (*pos & GENMASK_ULL(53, 44)) >> 44;  in amdgpu_debugfs_process_reg_op()
629 	offset = (*pos & GENMASK_ULL(6, 0));  in amdgpu_debugfs_wave_read()
630 	se = (*pos & GENMASK_ULL(14, 7)) >> 7;  in amdgpu_debugfs_wave_read()
631 	sh = (*pos & GENMASK_ULL(22, 15)) >> 15;  in amdgpu_debugfs_wave_read()
632 	cu = (*pos & GENMASK_ULL(30, 23)) >> 23;  in amdgpu_debugfs_wave_read()
633 	wave = (*pos & GENMASK_ULL(36, 31)) >> 31;  in amdgpu_debugfs_wave_read()
634 	simd = (*pos & GENMASK_ULL(44, 37)) >> 37;  in amdgpu_debugfs_wave_read()
701 	offset = *pos & GENMASK_ULL(11, 0);  in amdgpu_debugfs_gpr_read()
702 	se = (*pos & GENMASK_ULL(19, 12)) >> 12;  in amdgpu_debugfs_gpr_read()
703 	sh = (*pos & GENMASK_ULL(27, 20)) >> 20;  in amdgpu_debugfs_gpr_read()
704 	cu = (*pos & GENMASK_ULL(35, 28)) >> 28;  in amdgpu_debugfs_gpr_read()
705 	wave = (*pos & GENMASK_ULL(43, 36)) >> 36;  in amdgpu_debugfs_gpr_read()
706 	simd = (*pos & GENMASK_ULL(51, 44)) >> 44;  in amdgpu_debugfs_gpr_read()
707 	thread = (*pos & GENMASK_ULL(59, 52)) >> 52;  in amdgpu_debugfs_gpr_read()
708 	bank = (*pos & GENMASK_ULL(61, 60)) >> 60;  in amdgpu_debugfs_gpr_read()