279 	struct i2s_platform_data *i2s_pdata;  in acp_hw_init()  local
329 	i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL);  in acp_hw_init()
330 	if (i2s_pdata == NULL) {  in acp_hw_init()
338 		i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |  in acp_hw_init()
342 		i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;  in acp_hw_init()
344 	i2s_pdata[0].cap = DWC_I2S_PLAY;  in acp_hw_init()
345 	i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;  in acp_hw_init()
346 	i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;  in acp_hw_init()
347 	i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;  in acp_hw_init()
350 		i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |  in acp_hw_init()
355 		i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |  in acp_hw_init()
359 	i2s_pdata[1].cap = DWC_I2S_RECORD;  in acp_hw_init()
360 	i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;  in acp_hw_init()
361 	i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;  in acp_hw_init()
362 	i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;  in acp_hw_init()
364 	i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;  in acp_hw_init()
367 		i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;  in acp_hw_init()
373 	i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;  in acp_hw_init()
374 	i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;  in acp_hw_init()
375 	i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;  in acp_hw_init()
376 	i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;  in acp_hw_init()
412 	adev->acp.acp_cell[1].platform_data = &i2s_pdata[0];  in acp_hw_init()
418 	adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];  in acp_hw_init()
424 	adev->acp.acp_cell[3].platform_data = &i2s_pdata[2];  in acp_hw_init()