160 static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)  in zynq_gpio_is_zynq()  argument
162 	return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);  in zynq_gpio_is_zynq()
171 static int gpio_data_ro_bug(struct zynq_gpio *gpio)  in gpio_data_ro_bug()  argument
173 	return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);  in gpio_data_ro_bug()
191 					  struct zynq_gpio *gpio)  in zynq_gpio_get_bank_pin()  argument
195 	for (bank = 0; bank < gpio->p_data->max_bank; bank++) {  in zynq_gpio_get_bank_pin()
196 		if ((pin_num >= gpio->p_data->bank_min[bank]) &&  in zynq_gpio_get_bank_pin()
197 		    (pin_num <= gpio->p_data->bank_max[bank])) {  in zynq_gpio_get_bank_pin()
200 					gpio->p_data->bank_min[bank];  in zynq_gpio_get_bank_pin()
224 	struct zynq_gpio *gpio = gpiochip_get_data(chip);  in zynq_gpio_get_value()  local
226 	zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_get_value()
228 	if (gpio_data_ro_bug(gpio)) {  in zynq_gpio_get_value()
229 		if (zynq_gpio_is_zynq(gpio)) {  in zynq_gpio_get_value()
231 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
234 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
239 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
242 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
247 		data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
267 	struct zynq_gpio *gpio = gpiochip_get_data(chip);  in zynq_gpio_set_value()  local
269 	zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_set_value()
287 	writel_relaxed(state, gpio->base_addr + reg_offset);  in zynq_gpio_set_value()
304 	struct zynq_gpio *gpio = gpiochip_get_data(chip);  in zynq_gpio_dir_in()  local
306 	zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_dir_in()
312 	if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&  in zynq_gpio_dir_in()
317 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_in()
319 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_in()
341 	struct zynq_gpio *gpio = gpiochip_get_data(chip);  in zynq_gpio_dir_out()  local
343 	zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_dir_out()
346 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_out()
348 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_out()
351 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));  in zynq_gpio_dir_out()
353 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));  in zynq_gpio_dir_out()
371 	struct zynq_gpio *gpio =  in zynq_gpio_irq_mask()  local
375 	zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_irq_mask()
377 		       gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));  in zynq_gpio_irq_mask()
392 	struct zynq_gpio *gpio =  in zynq_gpio_irq_unmask()  local
396 	zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_irq_unmask()
398 		       gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));  in zynq_gpio_irq_unmask()
412 	struct zynq_gpio *gpio =  in zynq_gpio_irq_ack()  local
416 	zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_irq_ack()
418 		       gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));  in zynq_gpio_irq_ack()
463 	struct zynq_gpio *gpio =  in zynq_gpio_set_irq_type()  local
467 	zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_set_irq_type()
469 	int_type = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
471 	int_pol = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
473 	int_any = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
508 		       gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
510 		       gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
512 		       gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
528 	struct zynq_gpio *gpio =  in zynq_gpio_set_wake()  local
531 	irq_set_irq_wake(gpio->irq, on);  in zynq_gpio_set_wake()
560 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,  in zynq_gpio_handle_bank_irq()  argument
564 	unsigned int bank_offset = gpio->p_data->bank_min[bank_num];  in zynq_gpio_handle_bank_irq()
565 	struct irq_domain *irqdomain = gpio->chip.irq.domain;  in zynq_gpio_handle_bank_irq()
593 	struct zynq_gpio *gpio =  in zynq_gpio_irqhandler()  local
599 	for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {  in zynq_gpio_irqhandler()
600 		int_sts = readl_relaxed(gpio->base_addr +  in zynq_gpio_irqhandler()
602 		int_enb = readl_relaxed(gpio->base_addr +  in zynq_gpio_irqhandler()
604 		zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);  in zynq_gpio_irqhandler()
610 static void zynq_gpio_save_context(struct zynq_gpio *gpio)  in zynq_gpio_save_context()  argument
614 	for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {  in zynq_gpio_save_context()
615 		gpio->context.datalsw[bank_num] =  in zynq_gpio_save_context()
616 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
618 		gpio->context.datamsw[bank_num] =  in zynq_gpio_save_context()
619 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
621 		gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
623 		gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
625 		gpio->context.int_type[bank_num] =  in zynq_gpio_save_context()
626 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
628 		gpio->context.int_polarity[bank_num] =  in zynq_gpio_save_context()
629 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
631 		gpio->context.int_any[bank_num] =  in zynq_gpio_save_context()
632 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
637 static void zynq_gpio_restore_context(struct zynq_gpio *gpio)  in zynq_gpio_restore_context()  argument
641 	for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {  in zynq_gpio_restore_context()
642 		writel_relaxed(gpio->context.datalsw[bank_num],  in zynq_gpio_restore_context()
643 			       gpio->base_addr +  in zynq_gpio_restore_context()
645 		writel_relaxed(gpio->context.datamsw[bank_num],  in zynq_gpio_restore_context()
646 			       gpio->base_addr +  in zynq_gpio_restore_context()
648 		writel_relaxed(gpio->context.dirm[bank_num],  in zynq_gpio_restore_context()
649 			       gpio->base_addr +  in zynq_gpio_restore_context()
651 		writel_relaxed(gpio->context.int_en[bank_num],  in zynq_gpio_restore_context()
652 			       gpio->base_addr +  in zynq_gpio_restore_context()
654 		writel_relaxed(gpio->context.int_type[bank_num],  in zynq_gpio_restore_context()
655 			       gpio->base_addr +  in zynq_gpio_restore_context()
657 		writel_relaxed(gpio->context.int_polarity[bank_num],  in zynq_gpio_restore_context()
658 			       gpio->base_addr +  in zynq_gpio_restore_context()
660 		writel_relaxed(gpio->context.int_any[bank_num],  in zynq_gpio_restore_context()
661 			       gpio->base_addr +  in zynq_gpio_restore_context()
668 	struct zynq_gpio *gpio = dev_get_drvdata(dev);  in zynq_gpio_suspend()  local
669 	struct irq_data *data = irq_get_irq_data(gpio->irq);  in zynq_gpio_suspend()
672 		zynq_gpio_save_context(gpio);  in zynq_gpio_suspend()
681 	struct zynq_gpio *gpio = dev_get_drvdata(dev);  in zynq_gpio_resume()  local
682 	struct irq_data *data = irq_get_irq_data(gpio->irq);  in zynq_gpio_resume()
687 		zynq_gpio_restore_context(gpio);  in zynq_gpio_resume()
697 	struct zynq_gpio *gpio = platform_get_drvdata(pdev);  in zynq_gpio_runtime_suspend()  local
699 	clk_disable_unprepare(gpio->clk);  in zynq_gpio_runtime_suspend()
707 	struct zynq_gpio *gpio = platform_get_drvdata(pdev);  in zynq_gpio_runtime_resume()  local
709 	return clk_prepare_enable(gpio->clk);  in zynq_gpio_runtime_resume()
791 	struct zynq_gpio *gpio;  in zynq_gpio_probe()  local
796 	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);  in zynq_gpio_probe()
797 	if (!gpio)  in zynq_gpio_probe()
805 	gpio->p_data = match->data;  in zynq_gpio_probe()
806 	platform_set_drvdata(pdev, gpio);  in zynq_gpio_probe()
809 	gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);  in zynq_gpio_probe()
810 	if (IS_ERR(gpio->base_addr))  in zynq_gpio_probe()
811 		return PTR_ERR(gpio->base_addr);  in zynq_gpio_probe()
813 	gpio->irq = platform_get_irq(pdev, 0);  in zynq_gpio_probe()
814 	if (gpio->irq < 0) {  in zynq_gpio_probe()
816 		return gpio->irq;  in zynq_gpio_probe()
820 	chip = &gpio->chip;  in zynq_gpio_probe()
821 	chip->label = gpio->p_data->label;  in zynq_gpio_probe()
831 	chip->ngpio = gpio->p_data->ngpio;  in zynq_gpio_probe()
834 	gpio->clk = devm_clk_get(&pdev->dev, NULL);  in zynq_gpio_probe()
835 	if (IS_ERR(gpio->clk)) {  in zynq_gpio_probe()
837 		return PTR_ERR(gpio->clk);  in zynq_gpio_probe()
839 	ret = clk_prepare_enable(gpio->clk);  in zynq_gpio_probe()
852 	ret = gpiochip_add_data(chip, gpio);  in zynq_gpio_probe()
859 	for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)  in zynq_gpio_probe()
860 		writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +  in zynq_gpio_probe()
870 	gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq,  in zynq_gpio_probe()
883 	clk_disable_unprepare(gpio->clk);  in zynq_gpio_probe()
896 	struct zynq_gpio *gpio = platform_get_drvdata(pdev);  in zynq_gpio_remove()  local
899 	gpiochip_remove(&gpio->chip);  in zynq_gpio_remove()
900 	clk_disable_unprepare(gpio->clk);  in zynq_gpio_remove()