140 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset,  in sprd_eic_update()  argument
145 		sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);  in sprd_eic_update()
153 		tmp |= BIT(SPRD_EIC_BIT(offset));  in sprd_eic_update()
155 		tmp &= ~BIT(SPRD_EIC_BIT(offset));  in sprd_eic_update()
161 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg)  in sprd_eic_read()  argument
165 		sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);  in sprd_eic_read()
167 	return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset)));  in sprd_eic_read()
170 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset)  in sprd_eic_request()  argument
172 	sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1);  in sprd_eic_request()
176 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset)  in sprd_eic_free()  argument
178 	sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0);  in sprd_eic_free()
181 static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset)  in sprd_eic_get()  argument
183 	return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA);  in sprd_eic_get()
186 static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset)  in sprd_eic_direction_input()  argument
192 static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value)  in sprd_eic_set()  argument
197 static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset,  in sprd_eic_set_debounce()  argument
202 		sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);  in sprd_eic_set_debounce()
203 	u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4;  in sprd_eic_set_debounce()
212 static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset,  in sprd_eic_set_config()  argument
219 		return sprd_eic_set_debounce(chip, offset, arg);  in sprd_eic_set_config()
228 	u32 offset = irqd_to_hwirq(data);  in sprd_eic_irq_mask()  local
232 		sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0);  in sprd_eic_irq_mask()
233 		sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0);  in sprd_eic_irq_mask()
236 		sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0);  in sprd_eic_irq_mask()
239 		sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0);  in sprd_eic_irq_mask()
242 		sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0);  in sprd_eic_irq_mask()
253 	u32 offset = irqd_to_hwirq(data);  in sprd_eic_irq_unmask()  local
257 		sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1);  in sprd_eic_irq_unmask()
258 		sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1);  in sprd_eic_irq_unmask()
261 		sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1);  in sprd_eic_irq_unmask()
264 		sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1);  in sprd_eic_irq_unmask()
267 		sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1);  in sprd_eic_irq_unmask()
278 	u32 offset = irqd_to_hwirq(data);  in sprd_eic_irq_ack()  local
282 		sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);  in sprd_eic_irq_ack()
285 		sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);  in sprd_eic_irq_ack()
288 		sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);  in sprd_eic_irq_ack()
291 		sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);  in sprd_eic_irq_ack()
302 	u32 offset = irqd_to_hwirq(data);  in sprd_eic_irq_set_type()  local
309 			sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);  in sprd_eic_irq_set_type()
312 			sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);  in sprd_eic_irq_set_type()
317 			state = sprd_eic_get(chip, offset);  in sprd_eic_irq_set_type()
319 				sprd_eic_update(chip, offset,  in sprd_eic_irq_set_type()
322 				sprd_eic_update(chip, offset,  in sprd_eic_irq_set_type()
334 			sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);  in sprd_eic_irq_set_type()
337 			sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);  in sprd_eic_irq_set_type()
342 			state = sprd_eic_get(chip, offset);  in sprd_eic_irq_set_type()
344 				sprd_eic_update(chip, offset,  in sprd_eic_irq_set_type()
347 				sprd_eic_update(chip, offset,  in sprd_eic_irq_set_type()
359 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);  in sprd_eic_irq_set_type()
360 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);  in sprd_eic_irq_set_type()
361 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);  in sprd_eic_irq_set_type()
365 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);  in sprd_eic_irq_set_type()
366 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);  in sprd_eic_irq_set_type()
367 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);  in sprd_eic_irq_set_type()
371 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);  in sprd_eic_irq_set_type()
375 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);  in sprd_eic_irq_set_type()
376 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);  in sprd_eic_irq_set_type()
377 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);  in sprd_eic_irq_set_type()
381 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);  in sprd_eic_irq_set_type()
382 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);  in sprd_eic_irq_set_type()
383 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);  in sprd_eic_irq_set_type()
393 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);  in sprd_eic_irq_set_type()
394 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);  in sprd_eic_irq_set_type()
395 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);  in sprd_eic_irq_set_type()
399 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);  in sprd_eic_irq_set_type()
400 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);  in sprd_eic_irq_set_type()
401 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);  in sprd_eic_irq_set_type()
405 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);  in sprd_eic_irq_set_type()
409 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);  in sprd_eic_irq_set_type()
410 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);  in sprd_eic_irq_set_type()
411 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);  in sprd_eic_irq_set_type()
415 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);  in sprd_eic_irq_set_type()
416 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);  in sprd_eic_irq_set_type()
417 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);  in sprd_eic_irq_set_type()
432 				    unsigned int offset)  in sprd_eic_toggle_trigger()  argument
449 	state = sprd_eic_get(chip, offset);  in sprd_eic_toggle_trigger()
455 			sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);  in sprd_eic_toggle_trigger()
457 			sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);  in sprd_eic_toggle_trigger()
461 			sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);  in sprd_eic_toggle_trigger()
463 			sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);  in sprd_eic_toggle_trigger()
470 	post_state = sprd_eic_get(chip, offset);  in sprd_eic_toggle_trigger()