46 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)  in ath79_gpio_read()  argument
48 	return readl(ctrl->base + reg);  in ath79_gpio_read()
51 static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,  in ath79_gpio_write()  argument
54 	writel(val, ctrl->base + reg);  in ath79_gpio_write()
58 	struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)  in ath79_gpio_update_bits()  argument
62 	old_val = ath79_gpio_read(ctrl, reg);  in ath79_gpio_update_bits()
66 		ath79_gpio_write(ctrl, reg, new_val);  in ath79_gpio_update_bits()
73 	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);  in ath79_gpio_irq_unmask()  local
77 	raw_spin_lock_irqsave(&ctrl->lock, flags);  in ath79_gpio_irq_unmask()
78 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);  in ath79_gpio_irq_unmask()
79 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);  in ath79_gpio_irq_unmask()
84 	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);  in ath79_gpio_irq_mask()  local
88 	raw_spin_lock_irqsave(&ctrl->lock, flags);  in ath79_gpio_irq_mask()
89 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);  in ath79_gpio_irq_mask()
90 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);  in ath79_gpio_irq_mask()
95 	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);  in ath79_gpio_irq_enable()  local
99 	raw_spin_lock_irqsave(&ctrl->lock, flags);  in ath79_gpio_irq_enable()
100 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);  in ath79_gpio_irq_enable()
101 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);  in ath79_gpio_irq_enable()
102 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);  in ath79_gpio_irq_enable()
107 	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);  in ath79_gpio_irq_disable()  local
111 	raw_spin_lock_irqsave(&ctrl->lock, flags);  in ath79_gpio_irq_disable()
112 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);  in ath79_gpio_irq_disable()
113 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);  in ath79_gpio_irq_disable()
114 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);  in ath79_gpio_irq_disable()
120 	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);  in ath79_gpio_irq_set_type()  local
144 	raw_spin_lock_irqsave(&ctrl->lock, flags);  in ath79_gpio_irq_set_type()
147 		ctrl->both_edges |= mask;  in ath79_gpio_irq_set_type()
148 		polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);  in ath79_gpio_irq_set_type()
150 		ctrl->both_edges &= ~mask;  in ath79_gpio_irq_set_type()
158 		ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);  in ath79_gpio_irq_set_type()
161 		ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);  in ath79_gpio_irq_set_type()
163 		ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);  in ath79_gpio_irq_set_type()
167 			ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);  in ath79_gpio_irq_set_type()
169 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);  in ath79_gpio_irq_set_type()
187 	struct ath79_gpio_ctrl *ctrl =  in ath79_gpio_irq_handler()  local
195 	raw_spin_lock_irqsave(&ctrl->lock, flags);  in ath79_gpio_irq_handler()
197 	pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);  in ath79_gpio_irq_handler()
200 	both_edges = ctrl->both_edges & pending;  in ath79_gpio_irq_handler()
202 		state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);  in ath79_gpio_irq_handler()
203 		ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,  in ath79_gpio_irq_handler()
207 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);  in ath79_gpio_irq_handler()
229 	struct ath79_gpio_ctrl *ctrl;  in ath79_gpio_probe()  local
235 	ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);  in ath79_gpio_probe()
236 	if (!ctrl)  in ath79_gpio_probe()
238 	platform_set_drvdata(pdev, ctrl);  in ath79_gpio_probe()
263 	ctrl->base = devm_ioremap_nocache(  in ath79_gpio_probe()
265 	if (!ctrl->base)  in ath79_gpio_probe()
268 	raw_spin_lock_init(&ctrl->lock);  in ath79_gpio_probe()
269 	err = bgpio_init(&ctrl->gc, &pdev->dev, 4,  in ath79_gpio_probe()
270 			ctrl->base + AR71XX_GPIO_REG_IN,  in ath79_gpio_probe()
271 			ctrl->base + AR71XX_GPIO_REG_SET,  in ath79_gpio_probe()
272 			ctrl->base + AR71XX_GPIO_REG_CLEAR,  in ath79_gpio_probe()
273 			oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,  in ath79_gpio_probe()
274 			oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,  in ath79_gpio_probe()
281 	ctrl->gc.base = 0;  in ath79_gpio_probe()
283 	err = gpiochip_add_data(&ctrl->gc, ctrl);  in ath79_gpio_probe()
293 	err = gpiochip_irqchip_add(&ctrl->gc, &ath79_gpio_irqchip, 0,  in ath79_gpio_probe()
300 	gpiochip_set_chained_irqchip(&ctrl->gc, &ath79_gpio_irqchip,  in ath79_gpio_probe()
307 	gpiochip_remove(&ctrl->gc);  in ath79_gpio_probe()
313 	struct ath79_gpio_ctrl *ctrl = platform_get_drvdata(pdev);  in ath79_gpio_remove()  local
315 	gpiochip_remove(&ctrl->gc);  in ath79_gpio_remove()