Lines Matching refs:pvt
318 u64 (*get_tolm)(struct sbridge_pvt *pvt);
319 u64 (*get_tohm)(struct sbridge_pvt *pvt);
328 u8 (*get_node_id)(struct sbridge_pvt *pvt);
329 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
330 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
793 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt) in sbridge_get_tolm() argument
798 pci_read_config_dword(pvt->pci_sad1, TOLM, ®); in sbridge_get_tolm()
802 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt) in sbridge_get_tohm() argument
806 pci_read_config_dword(pvt->pci_sad1, TOHM, ®); in sbridge_get_tohm()
810 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt) in ibridge_get_tolm() argument
814 pci_read_config_dword(pvt->pci_br1, TOLM, ®); in ibridge_get_tolm()
819 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt) in ibridge_get_tohm() argument
823 pci_read_config_dword(pvt->pci_br1, TOHM, ®); in ibridge_get_tohm()
876 static enum mem_type get_memory_type(struct sbridge_pvt *pvt) in get_memory_type() argument
881 if (pvt->pci_ddrio) { in get_memory_type()
882 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, in get_memory_type()
895 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt) in haswell_get_memory_type() argument
901 if (!pvt->pci_ddrio) in haswell_get_memory_type()
904 pci_read_config_dword(pvt->pci_ddrio, in haswell_get_memory_type()
910 pci_read_config_dword(pvt->pci_ta, MCMTR, ®); in haswell_get_memory_type()
927 static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr) in knl_get_width() argument
933 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr) in sbridge_get_width() argument
961 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr) in ibridge_get_width() argument
970 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr) in broadwell_get_width() argument
976 static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt) in knl_get_memory_type() argument
982 static u8 get_node_id(struct sbridge_pvt *pvt) in get_node_id() argument
985 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); in get_node_id()
989 static u8 haswell_get_node_id(struct sbridge_pvt *pvt) in haswell_get_node_id() argument
993 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); in haswell_get_node_id()
997 static u8 knl_get_node_id(struct sbridge_pvt *pvt) in knl_get_node_id() argument
1001 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); in knl_get_node_id()
1006 static u64 haswell_get_tolm(struct sbridge_pvt *pvt) in haswell_get_tolm() argument
1010 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®); in haswell_get_tolm()
1014 static u64 haswell_get_tohm(struct sbridge_pvt *pvt) in haswell_get_tohm() argument
1019 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); in haswell_get_tohm()
1021 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); in haswell_get_tohm()
1027 static u64 knl_get_tolm(struct sbridge_pvt *pvt) in knl_get_tolm() argument
1031 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®); in knl_get_tolm()
1035 static u64 knl_get_tohm(struct sbridge_pvt *pvt) in knl_get_tohm() argument
1040 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, ®_lo); in knl_get_tohm()
1041 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, ®_hi); in knl_get_tohm()
1115 static int knl_get_tad(const struct sbridge_pvt *pvt, in knl_get_tad() argument
1128 pci_mc = pvt->knl.pci_mc0; in knl_get_tad()
1131 pci_mc = pvt->knl.pci_mc1; in knl_get_tad()
1309 static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes) in knl_get_dimm_capacity() argument
1336 pci_read_config_dword(pvt->knl.pci_cha[i], in knl_get_dimm_capacity()
1362 pci_read_config_dword(pvt->knl.pci_cha[i], in knl_get_dimm_capacity()
1385 for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) { in knl_get_dimm_capacity()
1389 pci_read_config_dword(pvt->pci_sad0, in knl_get_dimm_capacity()
1390 pvt->info.dram_rule[sad_rule], &dram_rule); in knl_get_dimm_capacity()
1397 sad_limit = pvt->info.sad_limit(dram_rule)+1; in knl_get_dimm_capacity()
1400 pci_read_config_dword(pvt->pci_sad0, in knl_get_dimm_capacity()
1401 pvt->info.interleave_list[sad_rule], &interleave_reg); in knl_get_dimm_capacity()
1407 first_pkg = sad_pkg(pvt->info.interleave_pkg, in knl_get_dimm_capacity()
1410 pkg = sad_pkg(pvt->info.interleave_pkg, in knl_get_dimm_capacity()
1454 if (knl_get_tad(pvt, in knl_get_dimm_capacity()
1536 struct sbridge_pvt *pvt = mci->pvt_info; in get_source_id() local
1539 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL || in get_source_id()
1540 pvt->info.type == KNIGHTS_LANDING) in get_source_id()
1541 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); in get_source_id()
1543 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); in get_source_id()
1545 if (pvt->info.type == KNIGHTS_LANDING) in get_source_id()
1546 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg); in get_source_id()
1548 pvt->sbridge_dev->source_id = SOURCE_ID(reg); in get_source_id()
1555 struct sbridge_pvt *pvt = mci->pvt_info; in __populate_dimms() local
1556 int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS in __populate_dimms()
1563 mtype = pvt->info.get_memory_type(pvt); in __populate_dimms()
1581 if (pvt->info.type == KNIGHTS_LANDING) { in __populate_dimms()
1583 if (!pvt->knl.pci_channel[i]) in __populate_dimms()
1587 if (!pvt->pci_tad[i]) in __populate_dimms()
1593 if (pvt->info.type == KNIGHTS_LANDING) { in __populate_dimms()
1594 pci_read_config_dword(pvt->knl.pci_channel[i], in __populate_dimms()
1597 pci_read_config_dword(pvt->pci_tad[i], in __populate_dimms()
1602 if (!IS_ECC_ENABLED(pvt->info.mcmtr)) { in __populate_dimms()
1604 pvt->sbridge_dev->source_id, in __populate_dimms()
1605 pvt->sbridge_dev->dom, i); in __populate_dimms()
1608 pvt->channel[i].dimms++; in __populate_dimms()
1610 ranks = numrank(pvt->info.type, mtr); in __populate_dimms()
1612 if (pvt->info.type == KNIGHTS_LANDING) { in __populate_dimms()
1626 pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j, in __populate_dimms()
1632 dimm->dtype = pvt->info.get_width(pvt, mtr); in __populate_dimms()
1637 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j); in __populate_dimms()
1647 struct sbridge_pvt *pvt = mci->pvt_info; in get_dimm_config() local
1652 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); in get_dimm_config()
1654 pvt->sbridge_dev->mc, in get_dimm_config()
1655 pvt->sbridge_dev->node_id, in get_dimm_config()
1656 pvt->sbridge_dev->source_id); in get_dimm_config()
1661 if (pvt->info.type == KNIGHTS_LANDING) { in get_dimm_config()
1663 pvt->mirror_mode = NON_MIRRORING; in get_dimm_config()
1664 pvt->is_cur_addr_mirrored = false; in get_dimm_config()
1666 if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0) in get_dimm_config()
1668 if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) { in get_dimm_config()
1673 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { in get_dimm_config()
1674 if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) { in get_dimm_config()
1678 pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21); in get_dimm_config()
1680 pvt->mirror_mode = ADDR_RANGE_MIRRORING; in get_dimm_config()
1685 if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) { in get_dimm_config()
1690 pvt->mirror_mode = FULL_MIRRORING; in get_dimm_config()
1693 pvt->mirror_mode = NON_MIRRORING; in get_dimm_config()
1698 if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) { in get_dimm_config()
1702 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { in get_dimm_config()
1705 pvt->is_lockstep = true; in get_dimm_config()
1709 pvt->is_lockstep = false; in get_dimm_config()
1711 if (IS_CLOSE_PG(pvt->info.mcmtr)) { in get_dimm_config()
1713 pvt->is_close_pg = true; in get_dimm_config()
1716 pvt->is_close_pg = false; in get_dimm_config()
1725 struct sbridge_pvt *pvt = mci->pvt_info; in get_memory_layout() local
1737 pvt->tolm = pvt->info.get_tolm(pvt); in get_memory_layout()
1738 tmp_mb = (1 + pvt->tolm) >> 20; in get_memory_layout()
1742 gb, (mb*1000)/1024, (u64)pvt->tolm); in get_memory_layout()
1745 pvt->tohm = pvt->info.get_tohm(pvt); in get_memory_layout()
1746 tmp_mb = (1 + pvt->tohm) >> 20; in get_memory_layout()
1750 gb, (mb*1000)/1024, (u64)pvt->tohm); in get_memory_layout()
1759 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { in get_memory_layout()
1761 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], in get_memory_layout()
1763 limit = pvt->info.sad_limit(reg); in get_memory_layout()
1775 show_dram_attr(pvt->info.dram_attr(reg)), in get_memory_layout()
1778 get_intlv_mode_str(reg, pvt->info.type), in get_memory_layout()
1782 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], in get_memory_layout()
1784 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); in get_memory_layout()
1786 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); in get_memory_layout()
1795 if (pvt->info.type == KNIGHTS_LANDING) in get_memory_layout()
1803 pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], ®); in get_memory_layout()
1827 if (!pvt->channel[i].dimms) in get_memory_layout()
1830 pci_read_config_dword(pvt->pci_tad[i], in get_memory_layout()
1847 if (!pvt->channel[i].dimms) in get_memory_layout()
1850 pci_read_config_dword(pvt->pci_tad[i], in get_memory_layout()
1857 tmp_mb = pvt->info.rir_limit(reg) >> 20; in get_memory_layout()
1868 pci_read_config_dword(pvt->pci_tad[i], in get_memory_layout()
1871 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6; in get_memory_layout()
1878 (u32)RIR_RNK_TGT(pvt->info.type, reg), in get_memory_layout()
1904 struct sbridge_pvt *pvt = mci->pvt_info; in get_memory_error_data() local
1925 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { in get_memory_error_data()
1929 if (addr >= (u64)pvt->tohm) { in get_memory_error_data()
1937 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { in get_memory_error_data()
1938 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], in get_memory_error_data()
1944 limit = pvt->info.sad_limit(reg); in get_memory_error_data()
1953 if (n_sads == pvt->info.max_sad) { in get_memory_error_data()
1958 *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule)); in get_memory_error_data()
1959 interleave_mode = pvt->info.interleave_mode(dram_rule); in get_memory_error_data()
1961 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], in get_memory_error_data()
1964 if (pvt->info.type == SANDY_BRIDGE) { in get_memory_error_data()
1965 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); in get_memory_error_data()
1967 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); in get_memory_error_data()
1975 pvt->sbridge_dev->mc, in get_memory_error_data()
2004 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { in get_memory_error_data()
2021 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); in get_memory_error_data()
2027 pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®); in get_memory_error_data()
2036 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); in get_memory_error_data()
2056 pvt = mci->pvt_info; in get_memory_error_data()
2062 pci_ha = pvt->pci_ha; in get_memory_error_data()
2086 if (pvt->is_chan_hash) in get_memory_error_data()
2113 pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset); in get_memory_error_data()
2115 if (pvt->mirror_mode == FULL_MIRRORING || in get_memory_error_data()
2116 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) { in get_memory_error_data()
2128 pvt->is_cur_addr_mirrored = true; in get_memory_error_data()
2131 pvt->is_cur_addr_mirrored = false; in get_memory_error_data()
2134 if (pvt->is_lockstep) in get_memory_error_data()
2169 pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®); in get_memory_error_data()
2174 limit = pvt->info.rir_limit(reg); in get_memory_error_data()
2191 if (pvt->is_close_pg) in get_memory_error_data()
2197 pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®); in get_memory_error_data()
2198 *rank = RIR_RNK_TGT(pvt->info.type, reg); in get_memory_error_data()
2406 struct sbridge_pvt *pvt = mci->pvt_info; in sbridge_mci_bind_devs() local
2418 pvt->pci_sad0 = pdev; in sbridge_mci_bind_devs()
2421 pvt->pci_sad1 = pdev; in sbridge_mci_bind_devs()
2424 pvt->pci_br0 = pdev; in sbridge_mci_bind_devs()
2427 pvt->pci_ha = pdev; in sbridge_mci_bind_devs()
2430 pvt->pci_ta = pdev; in sbridge_mci_bind_devs()
2433 pvt->pci_ras = pdev; in sbridge_mci_bind_devs()
2441 pvt->pci_tad[id] = pdev; in sbridge_mci_bind_devs()
2446 pvt->pci_ddrio = pdev; in sbridge_mci_bind_devs()
2459 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha || in sbridge_mci_bind_devs()
2460 !pvt->pci_ras || !pvt->pci_ta) in sbridge_mci_bind_devs()
2480 struct sbridge_pvt *pvt = mci->pvt_info; in ibridge_mci_bind_devs() local
2493 pvt->pci_ha = pdev; in ibridge_mci_bind_devs()
2497 pvt->pci_ta = pdev; in ibridge_mci_bind_devs()
2501 pvt->pci_ras = pdev; in ibridge_mci_bind_devs()
2513 pvt->pci_tad[id] = pdev; in ibridge_mci_bind_devs()
2518 pvt->pci_ddrio = pdev; in ibridge_mci_bind_devs()
2521 pvt->pci_ddrio = pdev; in ibridge_mci_bind_devs()
2524 pvt->pci_sad0 = pdev; in ibridge_mci_bind_devs()
2527 pvt->pci_br0 = pdev; in ibridge_mci_bind_devs()
2530 pvt->pci_br1 = pdev; in ibridge_mci_bind_devs()
2543 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 || in ibridge_mci_bind_devs()
2544 !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta) in ibridge_mci_bind_devs()
2566 struct sbridge_pvt *pvt = mci->pvt_info; in haswell_mci_bind_devs() local
2572 if (pvt->info.pci_vtd == NULL) in haswell_mci_bind_devs()
2574 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, in haswell_mci_bind_devs()
2585 pvt->pci_sad0 = pdev; in haswell_mci_bind_devs()
2588 pvt->pci_sad1 = pdev; in haswell_mci_bind_devs()
2592 pvt->pci_ha = pdev; in haswell_mci_bind_devs()
2596 pvt->pci_ta = pdev; in haswell_mci_bind_devs()
2600 pvt->pci_ras = pdev; in haswell_mci_bind_devs()
2612 pvt->pci_tad[id] = pdev; in haswell_mci_bind_devs()
2620 if (!pvt->pci_ddrio) in haswell_mci_bind_devs()
2621 pvt->pci_ddrio = pdev; in haswell_mci_bind_devs()
2634 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || in haswell_mci_bind_devs()
2635 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) in haswell_mci_bind_devs()
2651 struct sbridge_pvt *pvt = mci->pvt_info; in broadwell_mci_bind_devs() local
2657 if (pvt->info.pci_vtd == NULL) in broadwell_mci_bind_devs()
2659 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, in broadwell_mci_bind_devs()
2670 pvt->pci_sad0 = pdev; in broadwell_mci_bind_devs()
2673 pvt->pci_sad1 = pdev; in broadwell_mci_bind_devs()
2677 pvt->pci_ha = pdev; in broadwell_mci_bind_devs()
2681 pvt->pci_ta = pdev; in broadwell_mci_bind_devs()
2685 pvt->pci_ras = pdev; in broadwell_mci_bind_devs()
2697 pvt->pci_tad[id] = pdev; in broadwell_mci_bind_devs()
2702 pvt->pci_ddrio = pdev; in broadwell_mci_bind_devs()
2715 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || in broadwell_mci_bind_devs()
2716 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) in broadwell_mci_bind_devs()
2732 struct sbridge_pvt *pvt = mci->pvt_info; in knl_mci_bind_devs() local
2751 pvt->knl.pci_mc0 = pdev; in knl_mci_bind_devs()
2753 pvt->knl.pci_mc1 = pdev; in knl_mci_bind_devs()
2763 pvt->pci_sad0 = pdev; in knl_mci_bind_devs()
2767 pvt->pci_sad1 = pdev; in knl_mci_bind_devs()
2783 WARN_ON(pvt->knl.pci_cha[devidx] != NULL); in knl_mci_bind_devs()
2785 pvt->knl.pci_cha[devidx] = pdev; in knl_mci_bind_devs()
2808 WARN_ON(pvt->knl.pci_channel[devidx] != NULL); in knl_mci_bind_devs()
2809 pvt->knl.pci_channel[devidx] = pdev; in knl_mci_bind_devs()
2813 pvt->knl.pci_mc_info = pdev; in knl_mci_bind_devs()
2817 pvt->pci_ta = pdev; in knl_mci_bind_devs()
2827 if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 || in knl_mci_bind_devs()
2828 !pvt->pci_sad0 || !pvt->pci_sad1 || in knl_mci_bind_devs()
2829 !pvt->pci_ta) { in knl_mci_bind_devs()
2834 if (!pvt->knl.pci_channel[i]) { in knl_mci_bind_devs()
2841 if (!pvt->knl.pci_cha[i]) { in knl_mci_bind_devs()
2868 struct sbridge_pvt *pvt = mci->pvt_info; in sbridge_mce_output_error() local
2885 if (pvt->info.type != SANDY_BRIDGE) in sbridge_mce_output_error()
2943 if (pvt->info.type == KNIGHTS_LANDING) { in sbridge_mce_output_error()
2988 pvt = mci->pvt_info; in sbridge_mce_output_error()
3006 if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg) in sbridge_mce_output_error()
3048 struct sbridge_pvt *pvt; in sbridge_mce_check_error() local
3057 pvt = mci->pvt_info; in sbridge_mce_check_error()
3104 struct sbridge_pvt *pvt; in sbridge_unregister_mci() local
3113 pvt = mci->pvt_info; in sbridge_unregister_mci()
3131 struct sbridge_pvt *pvt; in sbridge_register_mci() local
3144 sizeof(*pvt)); in sbridge_register_mci()
3152 pvt = mci->pvt_info; in sbridge_register_mci()
3153 memset(pvt, 0, sizeof(*pvt)); in sbridge_register_mci()
3156 pvt->sbridge_dev = sbridge_dev; in sbridge_register_mci()
3167 pvt->info.type = type; in sbridge_register_mci()
3170 pvt->info.rankcfgr = IB_RANK_CFG_A; in sbridge_register_mci()
3171 pvt->info.get_tolm = ibridge_get_tolm; in sbridge_register_mci()
3172 pvt->info.get_tohm = ibridge_get_tohm; in sbridge_register_mci()
3173 pvt->info.dram_rule = ibridge_dram_rule; in sbridge_register_mci()
3174 pvt->info.get_memory_type = get_memory_type; in sbridge_register_mci()
3175 pvt->info.get_node_id = get_node_id; in sbridge_register_mci()
3176 pvt->info.rir_limit = rir_limit; in sbridge_register_mci()
3177 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3178 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3179 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3180 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); in sbridge_register_mci()
3181 pvt->info.interleave_list = ibridge_interleave_list; in sbridge_register_mci()
3182 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3183 pvt->info.get_width = ibridge_get_width; in sbridge_register_mci()
3191 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3194 pvt->info.rankcfgr = SB_RANK_CFG_A; in sbridge_register_mci()
3195 pvt->info.get_tolm = sbridge_get_tolm; in sbridge_register_mci()
3196 pvt->info.get_tohm = sbridge_get_tohm; in sbridge_register_mci()
3197 pvt->info.dram_rule = sbridge_dram_rule; in sbridge_register_mci()
3198 pvt->info.get_memory_type = get_memory_type; in sbridge_register_mci()
3199 pvt->info.get_node_id = get_node_id; in sbridge_register_mci()
3200 pvt->info.rir_limit = rir_limit; in sbridge_register_mci()
3201 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3202 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3203 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3204 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); in sbridge_register_mci()
3205 pvt->info.interleave_list = sbridge_interleave_list; in sbridge_register_mci()
3206 pvt->info.interleave_pkg = sbridge_interleave_pkg; in sbridge_register_mci()
3207 pvt->info.get_width = sbridge_get_width; in sbridge_register_mci()
3215 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3219 pvt->info.get_tolm = haswell_get_tolm; in sbridge_register_mci()
3220 pvt->info.get_tohm = haswell_get_tohm; in sbridge_register_mci()
3221 pvt->info.dram_rule = ibridge_dram_rule; in sbridge_register_mci()
3222 pvt->info.get_memory_type = haswell_get_memory_type; in sbridge_register_mci()
3223 pvt->info.get_node_id = haswell_get_node_id; in sbridge_register_mci()
3224 pvt->info.rir_limit = haswell_rir_limit; in sbridge_register_mci()
3225 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3226 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3227 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3228 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); in sbridge_register_mci()
3229 pvt->info.interleave_list = ibridge_interleave_list; in sbridge_register_mci()
3230 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3231 pvt->info.get_width = ibridge_get_width; in sbridge_register_mci()
3239 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3243 pvt->info.get_tolm = haswell_get_tolm; in sbridge_register_mci()
3244 pvt->info.get_tohm = haswell_get_tohm; in sbridge_register_mci()
3245 pvt->info.dram_rule = ibridge_dram_rule; in sbridge_register_mci()
3246 pvt->info.get_memory_type = haswell_get_memory_type; in sbridge_register_mci()
3247 pvt->info.get_node_id = haswell_get_node_id; in sbridge_register_mci()
3248 pvt->info.rir_limit = haswell_rir_limit; in sbridge_register_mci()
3249 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3250 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3251 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3252 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); in sbridge_register_mci()
3253 pvt->info.interleave_list = ibridge_interleave_list; in sbridge_register_mci()
3254 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3255 pvt->info.get_width = broadwell_get_width; in sbridge_register_mci()
3263 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3267 pvt->info.get_tolm = knl_get_tolm; in sbridge_register_mci()
3268 pvt->info.get_tohm = knl_get_tohm; in sbridge_register_mci()
3269 pvt->info.dram_rule = knl_dram_rule; in sbridge_register_mci()
3270 pvt->info.get_memory_type = knl_get_memory_type; in sbridge_register_mci()
3271 pvt->info.get_node_id = knl_get_node_id; in sbridge_register_mci()
3272 pvt->info.rir_limit = NULL; in sbridge_register_mci()
3273 pvt->info.sad_limit = knl_sad_limit; in sbridge_register_mci()
3274 pvt->info.interleave_mode = knl_interleave_mode; in sbridge_register_mci()
3275 pvt->info.dram_attr = dram_attr_knl; in sbridge_register_mci()
3276 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule); in sbridge_register_mci()
3277 pvt->info.interleave_list = knl_interleave_list; in sbridge_register_mci()
3278 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3279 pvt->info.get_width = knl_get_width; in sbridge_register_mci()
3286 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()