49 static int edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32)  in edac_pci_read_dword()  argument
53 	ret = pci_read_config_dword(dev, reg, val32);  in edac_pci_read_dword()
71 static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32)  in edac_pci_write_dword()  argument
75 	ret = pci_write_config_dword(dev, reg, val32);  in edac_pci_write_dword()
99 	u32 val32;  in amd8111_pci_bridge_init()  local
105 	edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);  in amd8111_pci_bridge_init()
106 	if (val32 & PCI_STSCMD_CLEAR_MASK)  in amd8111_pci_bridge_init()
107 		edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);  in amd8111_pci_bridge_init()
110 	edac_pci_read_dword(dev, REG_HT_LINK, &val32);  in amd8111_pci_bridge_init()
111 	if (val32 & HT_LINK_CLEAR_MASK)  in amd8111_pci_bridge_init()
112 		edac_pci_write_dword(dev, REG_HT_LINK, val32);  in amd8111_pci_bridge_init()
117 	edac_pci_read_dword(dev, REG_MEM_LIM, &val32);  in amd8111_pci_bridge_init()
118 	if (val32 & MEM_LIMIT_CLEAR_MASK)  in amd8111_pci_bridge_init()
119 		edac_pci_write_dword(dev, REG_MEM_LIM, val32);  in amd8111_pci_bridge_init()
122 	edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);  in amd8111_pci_bridge_init()
123 	if (val32 & PCI_INTBRG_CTRL_CLEAR_MASK)  in amd8111_pci_bridge_init()
124 		edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);  in amd8111_pci_bridge_init()
129 		edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);  in amd8111_pci_bridge_init()
130 		val32 |= PCI_STSCMD_SERREN;  in amd8111_pci_bridge_init()
131 		edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);  in amd8111_pci_bridge_init()
134 		edac_pci_read_dword(dev, REG_HT_LINK, &val32);  in amd8111_pci_bridge_init()
135 		val32 |= HT_LINK_CRCFEN;  in amd8111_pci_bridge_init()
136 		edac_pci_write_dword(dev, REG_HT_LINK, val32);  in amd8111_pci_bridge_init()
139 		edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);  in amd8111_pci_bridge_init()
140 		val32 |= PCI_INTBRG_CTRL_POLL_MASK;  in amd8111_pci_bridge_init()
141 		edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);  in amd8111_pci_bridge_init()
147 	u32 val32;  in amd8111_pci_bridge_exit()  local
152 		edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);  in amd8111_pci_bridge_exit()
153 		val32 &= ~PCI_STSCMD_SERREN;  in amd8111_pci_bridge_exit()
154 		edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);  in amd8111_pci_bridge_exit()
157 		edac_pci_read_dword(dev, REG_HT_LINK, &val32);  in amd8111_pci_bridge_exit()
158 		val32 &= ~HT_LINK_CRCFEN;  in amd8111_pci_bridge_exit()
159 		edac_pci_write_dword(dev, REG_HT_LINK, val32);  in amd8111_pci_bridge_exit()
162 		edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);  in amd8111_pci_bridge_exit()
163 		val32 &= ~PCI_INTBRG_CTRL_POLL_MASK;  in amd8111_pci_bridge_exit()
164 		edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);  in amd8111_pci_bridge_exit()
172 	u32 val32;  in amd8111_pci_bridge_check()  local
175 	edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);  in amd8111_pci_bridge_check()
176 	if (val32 & PCI_STSCMD_CLEAR_MASK) {  in amd8111_pci_bridge_check()
180 			(val32 & PCI_STSCMD_SSE) != 0,  in amd8111_pci_bridge_check()
181 			(val32 & PCI_STSCMD_RMA) != 0,  in amd8111_pci_bridge_check()
182 			(val32 & PCI_STSCMD_RTA) != 0);  in amd8111_pci_bridge_check()
184 		val32 |= PCI_STSCMD_CLEAR_MASK;  in amd8111_pci_bridge_check()
185 		edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);  in amd8111_pci_bridge_check()
191 	edac_pci_read_dword(dev, REG_HT_LINK, &val32);  in amd8111_pci_bridge_check()
192 	if (val32 & HT_LINK_LKFAIL) {  in amd8111_pci_bridge_check()
196 			(val32 & HT_LINK_LKFAIL) != 0);  in amd8111_pci_bridge_check()
198 		val32 |= HT_LINK_LKFAIL;  in amd8111_pci_bridge_check()
199 		edac_pci_write_dword(dev, REG_HT_LINK, val32);  in amd8111_pci_bridge_check()
205 	edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);  in amd8111_pci_bridge_check()
206 	if (val32 & PCI_INTBRG_CTRL_DTSTAT) {  in amd8111_pci_bridge_check()
210 			(val32 & PCI_INTBRG_CTRL_DTSTAT) != 0);  in amd8111_pci_bridge_check()
212 		val32 |= PCI_INTBRG_CTRL_DTSTAT;  in amd8111_pci_bridge_check()
213 		edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);  in amd8111_pci_bridge_check()
219 	edac_pci_read_dword(dev, REG_MEM_LIM, &val32);  in amd8111_pci_bridge_check()
220 	if (val32 & MEM_LIMIT_CLEAR_MASK) {  in amd8111_pci_bridge_check()
226 			(val32 & MEM_LIMIT_DPE)  != 0,  in amd8111_pci_bridge_check()
227 			(val32 & MEM_LIMIT_RSE)  != 0,  in amd8111_pci_bridge_check()
228 			(val32 & MEM_LIMIT_RMA)  != 0,  in amd8111_pci_bridge_check()
229 			(val32 & MEM_LIMIT_RTA)  != 0,  in amd8111_pci_bridge_check()
230 			(val32 & MEM_LIMIT_STA)  != 0,  in amd8111_pci_bridge_check()
231 			(val32 & MEM_LIMIT_MDPE) != 0);  in amd8111_pci_bridge_check()
233 		val32 |= MEM_LIMIT_CLEAR_MASK;  in amd8111_pci_bridge_check()
234 		edac_pci_write_dword(dev, REG_MEM_LIM, val32);  in amd8111_pci_bridge_check()