Lines Matching defs:amd64_pvt
324 struct amd64_pvt { struct
325 struct low_ops *ops;
328 struct pci_dev *F0, *F1, *F2, *F3, *F6;
330 u16 mc_node_id; /* MC index of this MC node */
331 u8 fam; /* CPU family */
332 u8 model; /* ... model */
333 u8 stepping; /* ... stepping */
335 int ext_model; /* extended model value of this node */
336 int channel_count;
339 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
340 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
341 u32 dchr0; /* DRAM Configuration High DCT0 reg */
342 u32 dchr1; /* DRAM Configuration High DCT1 reg */
343 u32 nbcap; /* North Bridge Capabilities */
344 u32 nbcfg; /* F10 North Bridge Configuration */
345 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
346 u32 dhar; /* DRAM Hoist reg */
347 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
348 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
351 struct chip_select csels[2];
354 struct dram_range ranges[DRAM_RANGES];
356 u64 top_mem; /* top of memory below 4GB */
357 u64 top_mem2; /* top of memory above 4GB */
359 u32 dct_sel_lo; /* DRAM Controller Select Low */
360 u32 dct_sel_hi; /* DRAM Controller Select High */
361 u32 online_spare; /* On-Line spare Reg */
364 u8 ecc_sym_sz;
367 struct error_injection injection;
370 enum mem_type dram_type;
372 struct amd64_umc *umc; /* UMC registers */