721 	if (pvt->umc) {  in determine_edac_cap()
725 			if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT))  in determine_edac_cap()
731 			if (pvt->umc[i].umc_cfg & BIT(12))  in determine_edac_cap()
810 	struct amd64_umc *umc;  in __dump_misc_regs_df()  local
815 		umc = &pvt->umc[i];  in __dump_misc_regs_df()
817 		edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);  in __dump_misc_regs_df()
818 		edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);  in __dump_misc_regs_df()
819 		edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);  in __dump_misc_regs_df()
820 		edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);  in __dump_misc_regs_df()
827 		edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);  in __dump_misc_regs_df()
830 				i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no",  in __dump_misc_regs_df()
831 				    (umc->umc_cap_hi & BIT(31)) ? "yes" : "no");  in __dump_misc_regs_df()
833 				i, (umc->umc_cfg & BIT(12)) ? "yes" : "no");  in __dump_misc_regs_df()
835 				i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no");  in __dump_misc_regs_df()
837 				i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no");  in __dump_misc_regs_df()
889 	if (pvt->umc)  in dump_misc_regs()
926 	if (pvt->umc) {  in read_dct_base_mask()
944 		if (pvt->umc) {  in read_dct_base_mask()
973 		if (pvt->umc) {  in read_dct_base_mask()
1047 		if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5))  in determine_memory_type()
1049 		else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4))  in determine_memory_type()
1390 		channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT);  in f17_early_channel_count()
1524 static int f17_base_addr_to_cs_size(struct amd64_pvt *pvt, u8 umc,  in f17_base_addr_to_cs_size()  argument
1527 	u32 base_addr = pvt->csels[umc].csbases[csrow_nr];  in f17_base_addr_to_cs_size()
1530 	u32 addr_mask = pvt->csels[umc].csmasks[csrow_nr >> 1];  in f17_base_addr_to_cs_size()
2530 	if (pvt->umc) {  in reserve_mc_sibling_devs()
2579 	if (pvt->umc) {  in free_mc_sibling_devs()
2592 	if (pvt->umc) {  in determine_ecc_sym_sz()
2597 			if ((pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) &&  in determine_ecc_sym_sz()
2598 			    (pvt->umc[i].ecc_ctrl & BIT(7))) {  in determine_ecc_sym_sz()
2627 	struct amd64_umc *umc;  in __read_mc_regs_df()  local
2634 		umc = &pvt->umc[i];  in __read_mc_regs_df()
2636 		amd_smn_read(nid, umc_base + UMCCH_DIMM_CFG, &umc->dimm_cfg);  in __read_mc_regs_df()
2637 		amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg);  in __read_mc_regs_df()
2638 		amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl);  in __read_mc_regs_df()
2639 		amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl);  in __read_mc_regs_df()
2640 		amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi);  in __read_mc_regs_df()
2669 	if (pvt->umc) {  in read_mc_regs()
2767 	if (!pvt->umc)  in get_csrow_nr_pages()
2796 	if (!pvt->umc) {  in init_csrows()
2841 		if (pvt->umc) {  in init_csrows()
3098 		if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {  in f17h_determine_edac_ctl_cap()
3099 			ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED);  in f17h_determine_edac_ctl_cap()
3100 			cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP);  in f17h_determine_edac_ctl_cap()
3121 	if (pvt->umc) {  in setup_mci_misc_attrs()
3242 		pvt->umc = kcalloc(NUM_UMCS, sizeof(struct amd64_umc), GFP_KERNEL);  in init_one_instance()
3243 		if (!pvt->umc) {  in init_one_instance()
3313 		kfree(pvt->umc);  in init_one_instance()
3415 	if (pvt->umc)  in setup_pci_device()