29        u32 scrubval;           /* bit pattern for scrub rate */  member
167 static inline void __f17h_set_scrubval(struct amd64_pvt *pvt, u32 scrubval)  in __f17h_set_scrubval()  argument
174 	if (scrubval >= 0x5 && scrubval <= 0x14) {  in __f17h_set_scrubval()
175 		scrubval -= 0x5;  in __f17h_set_scrubval()
176 		pci_write_bits32(pvt->F6, F17H_SCR_LIMIT_ADDR, scrubval, 0xF);  in __f17h_set_scrubval()
188 	u32 scrubval;  in __set_scrub_rate()  local
205 		if (scrubrates[i].scrubval < min_rate)  in __set_scrub_rate()
212 	scrubval = scrubrates[i].scrubval;  in __set_scrub_rate()
215 		__f17h_set_scrubval(pvt, scrubval);  in __set_scrub_rate()
218 		pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);  in __set_scrub_rate()
220 		pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);  in __set_scrub_rate()
222 		pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F);  in __set_scrub_rate()
225 	if (scrubval)  in __set_scrub_rate()
254 	u32 scrubval = 0;  in get_scrub_rate()  local
263 			amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval);  in get_scrub_rate()
267 		amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval);  in get_scrub_rate()
268 		if (scrubval & BIT(0)) {  in get_scrub_rate()
269 			amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval);  in get_scrub_rate()
270 			scrubval &= 0xF;  in get_scrub_rate()
271 			scrubval += 0x5;  in get_scrub_rate()
273 			scrubval = 0;  in get_scrub_rate()
278 		amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);  in get_scrub_rate()
282 	scrubval = scrubval & 0x001F;  in get_scrub_rate()
285 		if (scrubrates[i].scrubval == scrubval) {  in get_scrub_rate()