Lines Matching refs:and
4 # Licensed and distributed under the GPL
40 levels are 0-4 (from low to high) and by default it is set to 2.
68 It should be noticed that keeping both GHES and a hardware-driven
81 Support for error detection and correction of DRAM ECC errors on
88 Recent Opterons (Family 10h and later) provide for Memory Error
90 allows the operator/user to inject Uncorrectable and Correctable
100 In addition, there are two control files, inject_read and inject_write,
101 which trigger the DRAM ECC Read and Write respectively.
107 Support for error detection and correction on the AMD 76x
114 Support for error detection and correction on the Intel
115 E7205, E7500, E7501 and E7505 server chipsets.
118 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
121 Support for error detection and correction on the Intel
129 Support for error detection and correction on the Intel
136 Support for error detection and correction on the Intel
137 DP82785P and E7210 server chipsets.
143 Support for error detection and correction on the Intel
150 Support for error detection and correction on the Intel
151 3000 and 3010 server chipsets.
157 Support for error detection and correction on the Intel
158 3200 and 3210 server chipsets.
164 Support for error detection and correction on the Intel
171 Support for error detection and correction on the Intel
178 Support for error detection and correction the Intel
185 Support for error detection and correction the Intel
188 and Xeon 55xx processors.
194 Support for error detection and correction on the Intel
201 Support for error detection and correction on the Radisys
208 Support for error detection and correction the Intel
215 Support for error detection and correction the Intel
222 Support for error detection and correction the Intel
229 Support for error detection and correction the Intel
230 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
238 Support for error detection and correction the Intel
247 Support for error detection and correction on the Intel
249 first used on the Apollo Lake platform and Denverton
256 Support for error detection and correction on the Freescale
263 Support for error detection and correction on Freescale memory
270 Support for error detection and correction on the Marvell
271 MV64360 and MV64460 chipsets.
277 Support for error detection and correction on PA Semi
284 Support for error detection and correction on the
295 440SP, 440SPe, 460EX, 460GT and 460SX.
301 Support for error detection and correction on the
310 Support for error detection and correction on the
319 Support for error detection and correction on the
320 IBM CPC925 Bridge and Memory Controller, which is
328 Support for error detection and correction on the
335 Support for error detection and correction on the
342 Support for error detection and correction on the primary caches of
349 Support for error detection and correction on the
356 Support for error detection and correction on the
363 Support for error detection and correction on the
371 Support for error detection and correction on the
373 Coherent Processor Interconnect (CCPI) and L2 cache
380 Support for error detection and correction on the
389 Support for error detection and correction on the
397 Support for error detection and correction on the
404 Support for error detection and correction on the
411 Support for error detection and correction on the
418 Support for error detection and correction on the
425 Support for error detection and correction on the
432 Support for error detection and correction on the
439 Support for error detection and correction on the
446 Support for error detection and correction on the Synopsys DDR
453 Support for error detection and correction on the
460 Support for error detection and correction on the