478 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,  in dma_ctrl_write()  function
487 	dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);  in dma_ctrl_clr()
493 	dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);  in dma_ctrl_set()
528 		dma_ctrl_write(chan, reg, addr);  in xilinx_write()
1096 		dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,  in xilinx_vdma_start_transfer()
1125 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_vdma_start_transfer()
1146 		dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,  in xilinx_vdma_start_transfer()
1221 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);  in xilinx_cdma_start_transfer()
1252 		dma_ctrl_write(chan, XILINX_DMA_REG_BTT,  in xilinx_cdma_start_transfer()
1293 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_start_transfer()
1302 			dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,  in xilinx_dma_start_transfer()
1306 				dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,  in xilinx_dma_start_transfer()
1309 				dma_ctrl_write(chan,  in xilinx_dma_start_transfer()
1331 			dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,  in xilinx_dma_start_transfer()
1335 				dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,  in xilinx_dma_start_transfer()
1338 				dma_ctrl_write(chan,  in xilinx_dma_start_transfer()
1355 		dma_ctrl_write(chan, XILINX_DMA_REG_BTT,  in xilinx_dma_start_transfer()
1471 	dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,  in xilinx_dma_irq_handler()
1484 		dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,  in xilinx_dma_irq_handler()
1940 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_prep_dma_cyclic()
2073 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_terminate_all()
2145 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);  in xilinx_vdma_channel_set_config()