Lines Matching refs:dma_ctrl_read
473 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg) in dma_ctrl_read() function
487 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr); in dma_ctrl_clr()
493 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set); in dma_ctrl_set()
1056 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); in xilinx_dma_start()
1108 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_vdma_start_transfer()
1287 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_dma_start_transfer()
1420 dma_ctrl_read(chan, XILINX_DMA_REG_DMACR), in xilinx_dma_reset()
1421 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); in xilinx_dma_reset()
1467 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR); in xilinx_dma_irq_handler()
1492 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC), in xilinx_dma_irq_handler()
1493 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC)); in xilinx_dma_irq_handler()
1938 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_dma_prep_dma_cyclic()
2062 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); in xilinx_dma_terminate_all()
2071 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_dma_terminate_all()
2106 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_vdma_channel_set_config()