Lines Matching refs:edma_shadow0_write_array
379 static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, in edma_shadow0_write_array() function
446 edma_shadow0_write_array(ecc, SH_ICR, channel >> 5, in edma_setup_interrupt()
448 edma_shadow0_write_array(ecc, SH_IESR, channel >> 5, in edma_setup_interrupt()
451 edma_shadow0_write_array(ecc, SH_IECR, channel >> 5, in edma_setup_interrupt()
597 edma_shadow0_write_array(ecc, SH_ESR, j, mask); in edma_start()
606 edma_shadow0_write_array(ecc, SH_SECR, j, mask); in edma_start()
607 edma_shadow0_write_array(ecc, SH_EESR, j, mask); in edma_start()
620 edma_shadow0_write_array(ecc, SH_EECR, j, mask); in edma_stop()
621 edma_shadow0_write_array(ecc, SH_ECR, j, mask); in edma_stop()
622 edma_shadow0_write_array(ecc, SH_SECR, j, mask); in edma_stop()
626 edma_shadow0_write_array(ecc, SH_ICR, j, mask); in edma_stop()
645 edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask); in edma_pause()
654 edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask); in edma_resume()
663 edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask); in edma_trigger_channel()
677 edma_shadow0_write_array(ecc, SH_ECR, j, mask); in edma_clean_channel()
681 edma_shadow0_write_array(ecc, SH_SECR, j, mask); in edma_clean_channel()
1479 edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); in dma_irq_handler()
1586 edma_shadow0_write_array(ecc, SH_SECR, j, in dma_ccerr_handler()