196 	struct tegra_dma	*tdma;  member
239 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)  in tdma_write()  argument
241 	writel(val, tdma->base_addr + reg);  in tdma_write()
244 static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)  in tdma_read()  argument
246 	return readl(tdma->base_addr + reg);  in tdma_read()
369 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_global_pause()  local
371 	spin_lock(&tdma->global_lock);  in tegra_dma_global_pause()
373 	if (tdc->tdma->global_pause_count == 0) {  in tegra_dma_global_pause()
374 		tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);  in tegra_dma_global_pause()
379 	tdc->tdma->global_pause_count++;  in tegra_dma_global_pause()
381 	spin_unlock(&tdma->global_lock);  in tegra_dma_global_pause()
386 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_global_resume()  local
388 	spin_lock(&tdma->global_lock);  in tegra_dma_global_resume()
390 	if (WARN_ON(tdc->tdma->global_pause_count == 0))  in tegra_dma_global_resume()
393 	if (--tdc->tdma->global_pause_count == 0)  in tegra_dma_global_resume()
394 		tdma_write(tdma, TEGRA_APBDMA_GENERAL,  in tegra_dma_global_resume()
398 	spin_unlock(&tdma->global_lock);  in tegra_dma_global_resume()
404 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_pause()  local
406 	if (tdma->chip_data->support_channel_pause) {  in tegra_dma_pause()
418 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_resume()  local
420 	if (tdma->chip_data->support_channel_pause) {  in tegra_dma_resume()
460 	if (tdc->tdma->chip_data->support_separate_wcount_reg)  in tegra_dma_start()
501 	if (tdc->tdma->chip_data->support_separate_wcount_reg)  in tegra_dma_configure_for_next()
773 	if (tdc->tdma->chip_data->support_separate_wcount_reg)  in tegra_dma_terminate_all()
933 	if (tdc->tdma->chip_data->support_separate_wcount_reg)  in tegra_dma_prep_wcount()
1006 				(len > tdc->tdma->chip_data->max_dma_count)) {  in tegra_dma_prep_slave_sg()
1105 			(len > tdc->tdma->chip_data->max_dma_count)) {  in tegra_dma_prep_dma_cyclic()
1193 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_alloc_chan_resources()  local
1199 	ret = pm_runtime_get_sync(tdma->dev);  in tegra_dma_alloc_chan_resources()
1209 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_free_chan_resources()  local
1245 	pm_runtime_put(tdma->dev);  in tegra_dma_free_chan_resources()
1253 	struct tegra_dma *tdma = ofdma->of_dma_data;  in tegra_dma_of_xlate()  local
1258 		dev_err(tdma->dev, "Invalid slave id: %d\n", dma_spec->args[0]);  in tegra_dma_of_xlate()
1262 	chan = dma_get_any_slave_channel(&tdma->dma_dev);  in tegra_dma_of_xlate()
1311 	struct tegra_dma *tdma;  in tegra_dma_probe()  local
1322 	tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *  in tegra_dma_probe()
1324 	if (!tdma)  in tegra_dma_probe()
1327 	tdma->dev = &pdev->dev;  in tegra_dma_probe()
1328 	tdma->chip_data = cdata;  in tegra_dma_probe()
1329 	platform_set_drvdata(pdev, tdma);  in tegra_dma_probe()
1332 	tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);  in tegra_dma_probe()
1333 	if (IS_ERR(tdma->base_addr))  in tegra_dma_probe()
1334 		return PTR_ERR(tdma->base_addr);  in tegra_dma_probe()
1336 	tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);  in tegra_dma_probe()
1337 	if (IS_ERR(tdma->dma_clk)) {  in tegra_dma_probe()
1339 		return PTR_ERR(tdma->dma_clk);  in tegra_dma_probe()
1342 	tdma->rst = devm_reset_control_get(&pdev->dev, "dma");  in tegra_dma_probe()
1343 	if (IS_ERR(tdma->rst)) {  in tegra_dma_probe()
1345 		return PTR_ERR(tdma->rst);  in tegra_dma_probe()
1348 	spin_lock_init(&tdma->global_lock);  in tegra_dma_probe()
1362 	reset_control_assert(tdma->rst);  in tegra_dma_probe()
1364 	reset_control_deassert(tdma->rst);  in tegra_dma_probe()
1367 	tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);  in tegra_dma_probe()
1368 	tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);  in tegra_dma_probe()
1369 	tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);  in tegra_dma_probe()
1373 	INIT_LIST_HEAD(&tdma->dma_dev.channels);  in tegra_dma_probe()
1375 		struct tegra_dma_channel *tdc = &tdma->channels[i];  in tegra_dma_probe()
1377 		tdc->chan_addr = tdma->base_addr +  in tegra_dma_probe()
1397 		tdc->dma_chan.device = &tdma->dma_dev;  in tegra_dma_probe()
1400 				&tdma->dma_dev.channels);  in tegra_dma_probe()
1401 		tdc->tdma = tdma;  in tegra_dma_probe()
1415 	dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);  in tegra_dma_probe()
1416 	dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);  in tegra_dma_probe()
1417 	dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);  in tegra_dma_probe()
1419 	tdma->global_pause_count = 0;  in tegra_dma_probe()
1420 	tdma->dma_dev.dev = &pdev->dev;  in tegra_dma_probe()
1421 	tdma->dma_dev.device_alloc_chan_resources =  in tegra_dma_probe()
1423 	tdma->dma_dev.device_free_chan_resources =  in tegra_dma_probe()
1425 	tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;  in tegra_dma_probe()
1426 	tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;  in tegra_dma_probe()
1427 	tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |  in tegra_dma_probe()
1431 	tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |  in tegra_dma_probe()
1435 	tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);  in tegra_dma_probe()
1441 	tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;  in tegra_dma_probe()
1442 	tdma->dma_dev.device_config = tegra_dma_slave_config;  in tegra_dma_probe()
1443 	tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;  in tegra_dma_probe()
1444 	tdma->dma_dev.device_tx_status = tegra_dma_tx_status;  in tegra_dma_probe()
1445 	tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;  in tegra_dma_probe()
1447 	ret = dma_async_device_register(&tdma->dma_dev);  in tegra_dma_probe()
1455 					 tegra_dma_of_xlate, tdma);  in tegra_dma_probe()
1467 	dma_async_device_unregister(&tdma->dma_dev);  in tegra_dma_probe()
1470 		struct tegra_dma_channel *tdc = &tdma->channels[i];  in tegra_dma_probe()
1484 	struct tegra_dma *tdma = platform_get_drvdata(pdev);  in tegra_dma_remove()  local
1488 	dma_async_device_unregister(&tdma->dma_dev);  in tegra_dma_remove()
1490 	for (i = 0; i < tdma->chip_data->nr_channels; ++i) {  in tegra_dma_remove()
1491 		tdc = &tdma->channels[i];  in tegra_dma_remove()
1505 	struct tegra_dma *tdma = dev_get_drvdata(dev);  in tegra_dma_runtime_suspend()  local
1508 	tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);  in tegra_dma_runtime_suspend()
1509 	for (i = 0; i < tdma->chip_data->nr_channels; i++) {  in tegra_dma_runtime_suspend()
1510 		struct tegra_dma_channel *tdc = &tdma->channels[i];  in tegra_dma_runtime_suspend()
1522 		if (tdma->chip_data->support_separate_wcount_reg)  in tegra_dma_runtime_suspend()
1527 	clk_disable_unprepare(tdma->dma_clk);  in tegra_dma_runtime_suspend()
1534 	struct tegra_dma *tdma = dev_get_drvdata(dev);  in tegra_dma_runtime_resume()  local
1537 	ret = clk_prepare_enable(tdma->dma_clk);  in tegra_dma_runtime_resume()
1543 	tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);  in tegra_dma_runtime_resume()
1544 	tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);  in tegra_dma_runtime_resume()
1545 	tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);  in tegra_dma_runtime_resume()
1547 	for (i = 0; i < tdma->chip_data->nr_channels; i++) {  in tegra_dma_runtime_resume()
1548 		struct tegra_dma_channel *tdc = &tdma->channels[i];  in tegra_dma_runtime_resume()
1555 		if (tdma->chip_data->support_separate_wcount_reg)  in tegra_dma_runtime_resume()